Datasheet

Bits Name Description Type Reset
20:15 TREQ_SEL Select a Transfer Request signal.
The channel uses the transfer request signal to pace its
data transfer rate. Sources for TREQ signals are internal
(TIMERS) or external (DREQ, a Data Request from the
system).
0x0 to 0x3a -> select DREQ n as TREQ
0x3b -> Select Timer 0 as TREQ
0x3c -> Select Timer 1 as TREQ
0x3d -> Select Timer 2 as TREQ (Optional)
0x3e -> Select Timer 3 as TREQ (Optional)
0x3f -> Permanent request, for unpaced transfers.
RW 0x00
14:11 CHAIN_TO When this channel completes, it will trigger the channel
indicated by CHAIN_TO. Disable by setting CHAIN_TO =
(this channel).
Reset value is equal to channel number (so CHAIN_TO
disabled by default).
RW varies
10 RING_SEL Select whether RING_SIZE applies to read or write
addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE)
boundary. If 1, write addresses are wrapped.
RW 0x0
9:6 RING_SIZE Size of address wrap region. If 0, don’t wrap. For values n >
0, only the lower n bits of the address will change. This
wraps the address on a (1 << n) byte boundary, facilitating
access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This
can apply to either read or write addresses, based on value
of RING_SEL.
0x0 -> RING_NONE
RW 0x0
5 INCR_WRITE If 1, the write address increments with each transfer. If 0,
each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral
transfers.
RW 0x0
4 INCR_READ If 1, the read address increments with each transfer. If 0,
each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory
transfers.
RW 0x0
3:2 DATA_SIZE Set the size of each bus transfer (byte/halfword/word).
READ_ADDR and WRITE_ADDR advance by this amount
(1/2/4 bytes) with each transfer.
0x0 -> SIZE_BYTE
0x1 -> SIZE_HALFWORD
0x2 -> SIZE_WORD
RW 0x0
RP2040 Datasheet
4.2. DMA 431