Datasheet

Table 421.
CH0_CTRL_TRIG,
CH1_CTRL_TRIG, …,
CH10_CTRL_TRIG,
CH11_CTRL_TRIG
Registers
Bits Name Description Type Reset
31 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags.
The channel halts when it encounters any bus error, and
always raises its channel IRQ flag.
RO 0x0
30 READ_ERROR If 1, the channel received a read bus error. Write one to
clear.
READ_ADDR shows the approximate address where the
bus error was encountered (will not to be earlier, or more
than 3 transfers later)
WC 0x0
29 WRITE_ERROR If 1, the channel received a write bus error. Write one to
clear.
WRITE_ADDR shows the approximate address where the
bus error was encountered (will not to be earlier, or more
than 5 transfers later)
WC 0x0
28:25 Reserved. - - -
24 BUSY This flag goes high when the channel starts a new transfer
sequence, and low when the last transfer of that sequence
completes. Clearing EN while BUSY is high pauses the
channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag),
see CHAN_ABORT.
RO 0x0
23 SNIFF_EN If 1, this channel’s data transfers are visible to the sniff
hardware, and each transfer will advance the state of the
checksum. This only applies if the sniff hardware is
enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-
control- block basis.
RW 0x0
22 BSWAP Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two
bytes of each halfword are swapped. For word data, the
four bytes of each word are swapped to reverse order.
RW 0x0
21 IRQ_QUIET In QUIET mode, the channel does not generate IRQs at the
end of every transfer block. Instead, an IRQ is raised when
NULL is written to a trigger register, indicating the end of a
control block chain.
This reduces the number of interrupts to be serviced by the
CPU when transferring a DMA chain of many small control
blocks.
RW 0x0
RP2040 Datasheet
4.2. DMA 430