Datasheet

Description
DMA Channel N Read Address pointer
Table 418.
CH0_READ_ADDR,
CH1_READ_ADDR, …,
CH10_READ_ADDR,
CH11_READ_ADDR
Registers
Bits Name Description Type Reset
31:0 NONAME This register updates automatically each time a read
completes. The current value is the next address to be read
by this channel.
RW 0x00000000
CH0_WRITE_ADDR, CH1_WRITE_ADDR, …, CH10_WRITE_ADDR,
CH11_WRITE_ADDR Registers
Description
DMA Channel N Write Address pointer
Table 419.
CH0_WRITE_ADDR,
CH1_WRITE_ADDR, …,
CH10_WRITE_ADDR,
CH11_WRITE_ADDR
Registers
Bits Name Description Type Reset
31:0 NONAME This register updates automatically each time a write
completes. The current value is the next address to be
written by this channel.
RW 0x00000000
CH0_TRANS_COUNT, CH1_TRANS_COUNT, …, CH10_TRANS_COUNT,
CH11_TRANS_COUNT Registers
Description
DMA Channel N Transfer Count
Table 420.
CH0_TRANS_COUNT,
CH1_TRANS_COUNT,
…,
CH10_TRANS_COUNT,
CH11_TRANS_COUNT
Registers
Bits Name Description Type Reset
31:0 NONAME Program the number of bus transfers a channel will
perform before halting. Note that, if transfers are larger
than one byte in size, this is not equal to the number of
bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the
number of transfers remaining, updating automatically
each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer
counter. Each time this channel is triggered, the RELOAD
value is copied into the live transfer counter. The channel
can be started multiple times, and will perform the same
number of transfers each time, as programmed by most
recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If
TRANS_COUNT is used as a trigger, the written value is
used immediately as the length of the new transfer
sequence, as well as being written to RELOAD.
RW 0x00000000
CH0_CTRL_TRIG, CH1_CTRL_TRIG, …, CH10_CTRL_TRIG, CH11_CTRL_TRIG
Registers
Description
DMA Channel N Control and Status
RP2040 Datasheet
4.2. DMA 429