Datasheet

Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/interp/hello_interp/hello_interp.c Lines 121 - 142
121 void simple_blend3() {
122 puts("Simple blend 3:");
123
124 interp_config cfg = interp_default_config();
125 interp_config_blend(&cfg, true);
126 interp_set_config(interp0, 0, &cfg);
127
128 cfg = interp_default_config();
129 interp_set_config(interp0, 1, &cfg);
130
131 interp0->accum[1] = 128;
132 interp0->base01 = 0x30005000;
133 printf("0x%08x\n", (int) interp0->peek[1]);
134 interp0->base01 = 0xe000f000;
135 printf("0x%08x\n", (int) interp0->peek[1]);
136
137 interp_config_signed(&cfg, true);
138 interp_set_config(interp0, 1, &cfg);
139
140 interp0->base01 = 0xe000f000;
141 printf("0x%08x\n", (int) interp0->peek[1]);
142 }
This should print:
0x00004000
0x0000e800
0xffffe800
2.3.1.6.3. Clamp Mode
Clamp mode is available on INTERP1 on each core, and is enabled by the CTRL_LANE0_CLAMP control flag. In clamp mode, the
PEEK0/POP0 result is the lane value (shifted, masked, sign-extended ACCUM0) clamped between BASE0 and BASE1. In other
words, if the lane value is greater than BASE1, a value of BASE1 is produced; if less than BASE0, a value of BASE0 is produced;
otherwise, the value passes through. No addition is performed. The signedness of these comparisons is controlled by the
CTRL_LANE0_SIGNED flag.
Other than this, the interpolator behaves the same as in normal mode.
Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/interp/hello_interp/hello_interp.c Lines 188 - 206
188 void clamp() {
189 puts("Clamp:");
190 interp_config cfg = interp_default_config();
191 interp_config_clamp(&cfg, true);
192 interp_config_shift(&cfg, 2);
193 // set mask according to new position of sign bit..
194 interp_config_mask(&cfg, 0, 29);
195 // ...so that the shifted value is correctly sign extended
196 interp_config_signed(&cfg, true);
197 interp_set_config(interp1, 0, &cfg);
198
199 interp1->base[0] = 0;
200 interp1->base[1] = 255;
201
202 for (int i = -1024; i <= 1024; i += 256) {
RP2040 Datasheet
2.3. Processor subsystem 42