Datasheet

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Bit reversal
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Byte swap
These manipulations do not affect the CRC calculation, just how the data is presented in the result register.
4.2.5.3. Channel Abort
It is possible for a channel to get into an irrecoverable state: e.g. if commanded to transfer more data than a peripheral
will ever request, it will never complete. Clearing the CTRL.EN bit merely pauses the channel, and does not solve the
problem. This should not occur under normal circumstances, but it is important that there is a mechanism to recover
without simply hard-resetting the entire DMA block.
The CHAN_ABORT register forces channels to complete early. There is one bit for each channel, and writing a 1
terminates that channel. This clears the transfer counter and forces the channel into an inactive state. Channels do not
generate a normal completion interrupt when they are aborted.
Warning: the channel may already have a bus transfer in flight between the read and write master, and this transfer
cannot be revoked. Starting the channel again while old transfers are still in flight can cause loss of data. The channel bit
in the CHAN_ABORT register will stay high until the channel has reached a safe state; generally this takes only a few
cycles.
The correct procedure is to write a bitmap into CHAN_ABORT of the channels you wish to terminate, and then poll the
register until it reads all-zeroes.
4.2.5.4. Debug
Debug registers are available for each DMA channel to show the dreq counter DBG_CTDDREQ and next transfer count DBG_TCR.
These can also be used to reset a DMA channel if required.
4.2.6. Example Use Cases
TO DO: GRAHAM/LIAM: Show to do channel pingponging, with some diagrams.
TO DO: GRAHAM/LIAM: Show a simple example of how to do control blocks.
TO DO: GRAHAM/LIAM: Show a peripheral gather operation, with ( READ_ADDR , TRANS_COUNT ) control blocks.
4.2.7. List of Registers
Table 417. List of
DMA registers
Offset Name Info
0x000 CH0_READ_ADDR DMA Channel 0 Read Address pointer
0x004 CH0_WRITE_ADDR DMA Channel 0 Write Address pointer
0x008 CH0_TRANS_COUNT DMA Channel 0 Transfer Count
0x00c CH0_CTRL_TRIG DMA Channel 0 Control and Status
0x010 CH0_AL1_CTRL Alias for channel 0 CTRL register
0x014 CH0_AL1_READ_ADDR Alias for channel 0 READ_ADDR register
0x018 CH0_AL1_WRITE_ADDR Alias for channel 0 WRITE_ADDR register
0x01c CH0_AL1_TRANS_COUNT_TRIG Alias for channel 0 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
0x020 CH0_AL2_CTRL Alias for channel 0 CTRL register
RP2040 Datasheet
4.2. DMA 420