Datasheet

and peripheral to become desynchronised, and can cause corruption or loss of data.
Another caveat is that multiple channels should not be connected to the same DREQ.
4.2.4. Interrupts
Each channel can generate interrupts; these can be masked on a per-channel basis using the INTE0 or INTE1 registers.
There are two circumstances where a channel raises an interrupt request:
•
On the completion of each transfer sequence, if CTRL.IRQ_QUIET is disabled
•
On receiving a null trigger, if CTRL.IRQ_QUIET is enabled
The masked interrupt status is visible in the INTS registers; there is one bit for each channel. Interrupts are cleared by
writing a bit mask to INTS. One idiom for acknowledging interrupts is to read INTS and then write the same value back, so
only enabled interrupts are cleared.
The RP2040 DMA provides two system IRQs, with independent masking and status registers (e.g. INTE0, INTE1). Any
combination of channel interrupt requests can be routed to either system IRQ. For example:
•
Some channels can be given a higher priority in the system interrupt controller, if they have particularly tight timing
requirements
•
In multiprocessor systems, different channel interrupts can be routed independently to different cores
For debugging purposes, the INTF registers can force either IRQ to be asserted.
4.2.5. Additional Features
4.2.5.1. Pacing Timers
These allow transfer of data roughly once every $n$ clk_sys clocks instead of using external peripheral DREQ to trigger
transfers. A fractional (X/Y) divider is used, and will generate a maximum of 1 request per clk_sys cycle.
There are 4 timers available in RP2040. Each DMA is able to select any of these in CTRL.TREQ_SEL.
4.2.5.2. CRC Calculation
The DMA can watch data from a given channel passing through the data FIFO, and calculate checksums based on this
data. This a purely passive affair: the data is not altered by this hardware, only observed.
The feature is controlled via the SNIFF_CTRL and SNIFF_DATA registers, and can be enabled/disabled per DMA transfer via the
CTRL.SNIFF_EN field.
As this hardware cannot place backpressure on the FIFO, it must keep up with the DMA’s maximum transfer rate of 32
bits per clock.
The supported checksums are:
•
CRC-32, MSB-first and LSB-first
•
CRC-16-CCITT, MSB-first and LSB-first
•
Simple summation (add to 32 bit accumulator)
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Even parity
The result register is both readable and writable, so that the initial seed value can be set.
Bit/byte manipulations are available on the result which may aid specific use cases:
•
Bit inversion
RP2040 Datasheet
4.2. DMA 419