Datasheet

4.2.3.1. System DREQ Table
There is a global assignment of DREQ numbers to peripheral DREQ channels.
Table 416. DREQs
DREQ DREQ Channel DREQ DREQ Channel DREQ DREQ Channel DREQ DREQ Channel
0
DREQ_PIO0_TX0
10
DREQ_PIO1_TX2
20
DREQ_UART0_TX
30
DREQ_PWM_WRAP6
1
DREQ_PIO0_TX1
11
DREQ_PIO1_TX3
21
DREQ_UART0_RX
31
DREQ_PWM_WRAP7
2
DREQ_PIO0_TX2
12
DREQ_PIO1_RX0
22
DREQ_UART1_TX
32
DREQ_I2C0_TX
3
DREQ_PIO0_TX3
13
DREQ_PIO1_RX1
23
DREQ_UART1_RX
33
DREQ_I2C0_RX
4
DREQ_PIO0_RX0
14
DREQ_PIO1_RX2
24
DREQ_PWM_WRAP0
34
DREQ_I2C1_TX
5
DREQ_PIO0_RX1
15
DREQ_PIO1_RX3
25
DREQ_PWM_WRAP1
35
DREQ_I2C1_RX
6
DREQ_PIO0_RX2
16
DREQ_SPI0_TX
26
DREQ_PWM_WRAP2
36
DREQ_ADC
7
DREQ_PIO0_RX3
17
DREQ_SPI0_RX
27
DREQ_PWM_WRAP3
37
DREQ_XIP_STREAM
8
DREQ_PIO1_TX0
18
DREQ_SPI1_TX
28
DREQ_PWM_WRAP4
38
DREQ_XIP_SSITX
9
DREQ_PIO1_TX1
19
DREQ_SPI1_RX
29
DREQ_PWM_WRAP5
39
DREQ_XIP_SSIRX
4.2.3.2. Credit-based DREQ Scheme
The RP2040 DMA is designed for systems where:
•
The area and power cost of large peripheral data FIFOs is prohibitive
•
The bandwidth demands of individual peripherals may be high, e.g. >50% bus injection rate for short periods
•
Bus latency is low, but multiple masters may be competing for bus access
In addition, the DMA’s transfer FIFOs and dual-master structure permit multiple accesses to the same peripheral to be in
flight at once, to improve gross throughput. Choice of DREQ mechanism is therefore critical:
•
The traditional "turn on the tap" method can cause overflow if multiple writes are backed up in the TDF. Some
systems solve this by overprovisioning peripheral FIFOs and setting the DREQ threshold below the full level, but this
wastes precious area and power
•
The ARM-style single and burst handshake does not permit additional requests to be registered while the current
request is being served. This limits performance when FIFOs are very shallow.
The RP2040 DMA uses a credit-based DREQ mechanism. For each peripheral, the DMA attempts to keep as many
transfers in flight as the peripheral has capacity for. This enables full bus throughput (1 word per clock) through an 8-deep
peripheral FIFO with no possibility of overflow or underflow, in the absence of fabric latency or contention.
For each channel, the DMA maintains a counter. Each 1-clock pulse on the dreq signal will increment this counter
(saturating). When nonzero, the channel requests a transfer from the DMA’s internal arbiter, and the counter is
decremented when the transfer is issued to the address FIFOs. At this point the transfer is in flight, but has not yet
necessarily completed.
clk
1 1 20 0
dreq
chan count
chan issue
1
Figure 56. DREQ
counting
The effect is to upper bound the number of in-flight transfers based on the amount of room or data available in the
peripheral FIFO. In the steady state, this gives maximum throughput, but can’t underflow or underflow.
One caveat is that the user must not access a FIFO which is currently being serviced by the DMA. This causes the channel
RP2040 Datasheet
4.2. DMA 418