Datasheet

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The value 0 is written to the trigger register. (This is useful for ending control block chains. See null triggers, Section
4.2.2.3)
4.2.2.2. Chaining
When a channel completes, it can name a different channel to immediately be triggered. This can be used as a callback
for the second channel to reconfigure and restart the first.
This feature is configured through the CHAIN_TO field in the channel CTRL register. This 4-bit value selects a a channel that
will start when this one finishes. A channel can not chain to itself. Setting CHAIN_TO to a channel’s own index means no
chaining will take place.
Chain triggers behave the same as triggers from other sources, such as trigger registers. For example, they cause
TRANS_COUNT to reload, and they are ignored if the targeted channel is already running.
TO DO: GRAHAM/LIAM: this next paragraph should be a code sample:
One application is for a channel to request reconfiguration by another channel, from a sequence of control blocks in
memory. Channel A is configured to perform a wrapped transfer from memory to channel B’s control registers (including
a trigger register), and channel B is configured to chain back to channel A when it completes each transfer sequence.
Use of the register aliases (section Section 4.2.2.1) enables compact formats for DMA control blocks: as little as one word
in some cases.
Another use of chaining is a "ping-pong" configuration, where two channels each trigger one another. The processor can
respond to the channel completion interrupts, and reconfigure each channel after it completes; however, the chained
channel, which has already been configured, starts immediately. In other words, channel configuration and channel
operation are pipelined. Performance can improve dramatically where many short transfer sequences are required.
Section Section 4.2.6 goes into more detail on the possibilities of chain triggers, in the real world.
4.2.2.3. Null Triggers and Chain Interrupts
As mentioned in Section 4.2.2.1, writing all-zeroes to a trigger register does not start the channel. This is called a null
trigger, and it has two purposes:
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Cause a halt at the end of an array of control blocks, by appending an all-zeroes block
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Reduce the number of interrupts generated when control blocks are used
By default, a channel will generate an interrupt each time it finishes a transfer sequence, unless that channel’s IRQ is
masked in INTE0 or INTE1. The rate of interrupts can be excessive, particularly as processor attention is generally not
required while a sequence of control blocks are in progress; however, processor attention is required at the end of a chain.
The channel CTRL register has a field called IRQ_QUIET. Its default value is 0. When this set to 1, channels generate an
interrupt when they receive a null trigger, and at no other time. The interrupt is generated by the channel which receives
the trigger.
4.2.3. Data Request (DREQ)
Peripherals produce or consume data at their own pace. If the DMA simply transferred data as fast as possible, loss or
corruption of data would ensue. DREQs are a communication channel between peripherals and the DMA, which enables
the DMA to pace transfers according to the needs of the peripheral.
The CTRL.TREQ_SEL (transfer request) field selects an external DREQ. It can also be used to select one of the internal pacing
timers, or select no TREQ at all (the transfer proceeds as fast as possible), e.g. for memory-to-memory transfers.
RP2040 Datasheet
4.2. DMA 417