Datasheet

transfer. For example:
•
If the address does not increment (e.g. it is the address of a peripheral FIFO), and the next transfer sequence is
to/from that same address, there is no need to write to the register again.
•
When transferring to/from a consecutive series of buffers in memory (e.g. scattering and gathering), an address
register will already have incremented to the start of the next buffer at the completion of a transfer.
By not programming all four CSRs for each transfer sequence, software can use shorter interrupt handlers, and more
compact control block formats when used with channel chaining (see register aliases in Section 4.2.2.1, chaining in
Section 4.2.2.2).

CAUTION
READ_ADDR and WRITE_ADDR must always be aligned to the current transfer size, as specified in CTRL.DATA_SIZE. It is up to
software to ensure the initial values are correctly aligned.
4.2.1.2. Transfer Count
Reading from TRANS_COUNT yields the number of transfers remaining in the current transfer sequence. This value updates
continuously as the channel progresses. Writing to TRANS_COUNT sets the length of the next transfer sequence. Up to
transfers can be performed in one sequence.
Each time the channel starts a new transfer sequence, the most recent value written to TRANS_COUNT is copied to the live
transfer counter, which will then start to decrement again as the new transfer sequence makes progress. For debugging
purposes, the last value written can be read from the DBG_TCR (TRANS_COUNT reload value) register.
If the channel is triggered multiple times without intervening writes to TRANS_COUNT, it performs the same number of
transfers each time. For example, when chained to, one channel might load a fixed-size control block into another
channel’s CSRs. TRANS_COUNT would be programmed once by software, and then reload automatically every time.
Alternatively, TRANS_COUNT can be written with a new value before starting each transfer sequence. If TRANS_COUNT is the
channel trigger (see Section 4.2.2.1), the channel will start immediately, and the value just written will be used, not the
value currently in the reload register.

NOTE
the TRANS_COUNT is the number of transfers to be performed. The total number of bytes transferred is TRANS_COUNT times
the size of each transfer in bytes, given by CTRL.DATA_SIZE.
4.2.1.3. Control/Status
The CTRL register has more, smaller fields than the other 3 registers, and full details of these are given in the CTRL register
listings. Among other things, CTRL is used to:
•
Configure the size of this channel’s data transfers, via CTRL.DATA_SIZE. Reads and writes are the same size.
•
Configure if and how READ_ADDR and WRITE_ADDR increment after each read or write, via CTRL.INCR_WRITE, CTRL.INCR_READ,
CTRL.RING_SEL, CTRL.RING_SIZE. Ring transfers are available, where one of the address pointers wraps at some power-
of-2 boundary.
•
Select another channel (or none) to be triggered when this channel completes, via CTRL.CHAIN_TO.
•
Select a peripheral data request (DREQ) signal to pace this channel’s transfers, via CTRL.TREQ_SEL.
•
See when the channel is idle, via CTRL.BUSY.
•
See if the channel has encountered a bus error, e.g. due to a faulty address being accessed, via CTRL.AHB_ERROR,
CTRL.READ_ERROR, or CTRL.WRITE_ERROR.
RP2040 Datasheet
4.2. DMA 415