Datasheet

Table Of Contents
Figure 55. DMA
Architecture Overview.
The read master can
read data from some
address every clock
cycle. Likewise, the
write master can write
to another address.
The address generator
produces matched
pairs of read and write
addresses, which the
masters consume
through the address
FIFOs. Up to 12
transfer sequences
may be in progress
simultaneously,
supervised by
software via the
control and status
registers.
The DMA can perform one read access and one write access, up to 32 bits in size, every clock cycle. There are 12
independent channels, each which supervise a sequence of bus transfers, usually in one of the following scenarios:
Memory-to-peripheral: a peripheral signals the DMA when it needs more data to transmit. The DMA reads data from
an array in RAM or flash, and writes to the peripheral’s data FIFO.
Peripheral-to-memory: a peripheral signals the DMA when it has received data. The DMA reads this data from the
peripheral’s data FIFO, and writes it to an array in RAM.
Memory-to-memory: the DMA transfers data between two buffers in RAM, as fast as possible.
Each channel has its own control and status registers (CSRs), with which software can program and monitor the
channel’s progress. When multiple channels are active at the same time, the DMA shares bandwidth evenly between the
channels, with round-robin over all channels which are currently requesting data transfers.
The transfer size can be either 32, 16, or 8 bits. This is configured once per channel: source transfer size and destination
transfer size are the same. The DMA performs standard byte lane replication on narrow writes, so byte data is available in
all 4 bytes of the databus, and halfword data in both halfwords.
Channels can be combined in varied ways for more sophisticated behaviour and greater autonomy. For example, one
channel can configure another, loading configuration data from a sequence of control blocks in memory, and the second
can then call back to the first via the CHAIN_TO option, when it needs to be reconfigured.
Making the DMA more autonomous means that much less processor supervision is required: overall this allows the
system to do more at once, or to dissipate less power.
4.2.1. Configuring Channels
Each channel has four control/status registers:
READ_ADDR is a pointer to the next address to be read from
WRITE_ADDR is a pointer to the next address to be written to
TRANS_COUNT shows the number of transfers remaining in the current transfer sequence, and is used to program the
number of transfers in the next transfer sequence (see Section 4.2.1.2).
CTRL is used to configure all other aspects of the channel’s behaviour, to enable/disable it, and to check for
completion.
These are live registers: they update continuously as the channel progresses.
4.2.1.1. Read and Write Addresses
READ_ADDR and WRITE_ADDR contain the address the channel will next read from, and write to, respectively. These registers
update automatically after each read/write access. They increment by 1, 2 or 4 bytes at a time, depending on the transfer
size configured in CTRL.
Software should generally program these registers with new start addresses each time a new transfer sequence starts. If
READ_ADDR and WRITE_ADDR are not reprogrammed, the DMA will use the current values as start addresses for the next
RP2040 Datasheet
4.2. DMA 414