Datasheet

BUFF_STATUS Register
Description
Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is
enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the
next clock cycle.
Table 399.
BUFF_STATUS
Register
Bits Name Description Type Reset
31 EP15_OUT RO 0x0
30 EP15_IN RO 0x0
29 EP14_OUT RO 0x0
28 EP14_IN RO 0x0
27 EP13_OUT RO 0x0
26 EP13_IN RO 0x0
25 EP12_OUT RO 0x0
24 EP12_IN RO 0x0
23 EP11_OUT RO 0x0
22 EP11_IN RO 0x0
21 EP10_OUT RO 0x0
20 EP10_IN RO 0x0
19 EP9_OUT RO 0x0
18 EP9_IN RO 0x0
17 EP8_OUT RO 0x0
16 EP8_IN RO 0x0
15 EP7_OUT RO 0x0
14 EP7_IN RO 0x0
13 EP6_OUT RO 0x0
12 EP6_IN RO 0x0
11 EP5_OUT RO 0x0
10 EP5_IN RO 0x0
9 EP4_OUT RO 0x0
8 EP4_IN RO 0x0
7 EP3_OUT RO 0x0
6 EP3_IN RO 0x0
5 EP2_OUT RO 0x0
4 EP2_IN RO 0x0
3 EP1_OUT RO 0x0
2 EP1_IN RO 0x0
1 EP0_OUT RO 0x0
RP2040 Datasheet
4.1. USB 401