Datasheet

Offset Name Info
0x8c INTR Raw Interrupts
0x90 INTE Interrupt Enable
0x94 INTF Interrupt Force
0x98 INTS Interrupt status after masking & forcing
ADDR_ENDP Register
Description
Device address and endpoint control
Table 391.
ADDR_ENDP Register
Bits Name Description Type Reset
31:20 Reserved. - - -
19:16 ENDPOINT Device endpoint to send data to. Only valid for HOST mode. RW 0x0
15:7 Reserved. - - -
6:0 ADDRESS In device mode, the address that the device should respond
to. Set in response to a SET_ADDR setup packet from the
host. In host mode set to the address of the device to
communicate with.
RW 0x00
ADDR_ENDP1, ADDR_ENDP2, …, ADDR_ENDP14, ADDR_ENDP15 Registers
Description
Interrupt endpoint N. Only valid for HOST mode.
Table 392.
ADDR_ENDP1,
ADDR_ENDP2, …,
ADDR_ENDP14,
ADDR_ENDP15
Registers
Bits Name Description Type Reset
31:27 Reserved. - - -
26 INTEP_PREAMBLE Interrupt EP requires preamble (is a low speed device on a
full speed hub)
RW 0x0
25 INTEP_DIR Direction of the interrupt endpoint. In=0, Out=1 RW 0x0
24:20 Reserved. - - -
19:16 ENDPOINT Endpoint number of the interrupt endpoint RW 0x0
15:7 Reserved. - - -
6:0 ADDRESS Device address RW 0x00
MAIN_CTRL Register
Description
Main control register
Table 393.
MAIN_CTRL Register
Bits Name Description Type Reset
31 SIM_TIMING Reduced timings for simulation RW 0x0
30:2 Reserved. - - -
1 HOST_NDEVICE Device mode = 0, Host mode = 1 RW 0x0
0 CONTROLLER_EN Enable controller RW 0x0
RP2040 Datasheet
4.1. USB 397