Datasheet

Offset Name Info
0x3c ADDR_ENDP15 Interrupt endpoint 15. Only valid for HOST mode.
0x40 MAIN_CTRL Main control register
0x44 SOF_WR Set the SOF (Start of Frame) frame number in the host controller.
The SOF packet is sent every 1ms and the host will increment the
frame number by 1 each time.
0x48 SOF_RD Read the last SOF (Start of Frame) frame number seen. In device
mode the last SOF received from the host. In host mode the last
SOF sent by the host.
0x4c SIE_CTRL SIE control register
0x50 SIE_STATUS SIE status register
0x54 INT_EP_CTRL interrupt endpoint control register
0x58 BUFF_STATUS Buffer status register. A bit set here indicates that a buffer has
completed on the endpoint (if the buffer interrupt is enabled). It is
possible for 2 buffers to be completed, so clearing the buffer
status bit may instantly re set it on the next clock cycle.
0x5c BUFF_CPU_SHOULD_HANDLE Which of the double buffers should be handled. Only valid if using
an interrupt per buffer (i.e. not per 2 buffers). Not valid for host
interrupt endpoint polling because they are only single buffered.
0x60 EP_ABORT Device only: Can be set to ignore the buffer control register for this
endpoint in case you would like to revoke a buffer. A NAK will be
sent for every access to the endpoint until this bit is cleared. A
corresponding bit in EP_ABORT_DONE is set when it is safe to modify
the buffer control register.
0x64 EP_ABORT_DONE
Device only: Used in conjunction with EP_ABORT. Set once an
endpoint is idle so the programmer knows it is safe to modify the
buffer control register.
0x68 EP_STALL_ARM
Device: this bit must be set in conjunction with the STALL bit in the
buffer control register to send a STALL on EP0. The device
controller clears these bits when a SETUP packet is received
because the USB spec requires that a STALL condition is cleared
when a SETUP packet is received.
0x6c NAK_POLL Used by the host controller. Sets the wait time in microseconds
before trying again if the device replies with a NAK.
0x70 EP_STATUS_STALL_NAK
Device: bits are set when the IRQ_ON_NAK or IRQ_ON_STALL bits are
set. For EP0 this comes from SIE_CTRL. For all other endpoints it
comes from the endpoint control register.
0x74 USB_MUXING Where to connect the USB controller. Should be to_phy by default.
0x78 USB_PWR Overrides for the power signals in the event that the VBUS signals
are not hooked up to GPIO. Set the value of the override and then
the override enable to switch over to the override value.
0x7c USBPHY_DIRECT This register allows for direct control of the USB phy. Use in
conjunction with usbphy_direct_override register to enable each
override bit.
0x80 USBPHY_DIRECT_OVERRIDE Override enable for each control in usbphy_direct
0x84 USBPHY_TRIM Used to adjust trim values of USB phy pull down resistors.
RP2040 Datasheet
4.1. USB 396