Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.4.1. Features
- 2.4.2. Functional Description
- 2.4.3. Programmer’s model
- 2.4.4. System control
- 2.4.5. NVIC
- 2.4.6. MPU
- 2.4.7. Debug
- 2.4.8. List of Registers
- 2.5. Memory
- 2.6. Boot Sequence
- 2.7. Bootrom
- 2.7.1. Bootrom Source
- 2.7.2. Processor Controlled Boot Sequence
- 2.7.3. Bootrom Contents
- 2.7.4. USB Mass Storage Interface
- 2.7.5. USB PICOBOOT Interface
- 2.8. Power Supplies
- 2.9. On-Chip Voltage Regulator
- 2.10. Power Control
- 2.11. Chip-Level Reset
- 2.12. Power-On State Machine
- 2.13. Subsystem Resets
- 2.14. Clocks
- 2.14.1. Overview
- 2.14.2. Clock sources
- 2.14.2.1. Ring Oscillator
- 2.14.2.1.1. Mitigating ROSC frequency variation due to process
- 2.14.2.1.2. Mitigating ROSC frequency variation due to voltage
- 2.14.2.1.3. Mitigating ROSC frequency variation due to temperature
- 2.14.2.1.4. Automatic mitigation of ROSC frequency variation due to PVT
- 2.14.2.1.5. Automatic overclocking using the ROSC
- 2.14.2.2. Crystal Oscillator
- 2.14.2.3. External Clocks
- 2.14.2.4. Relaxation Oscillators
- 2.14.2.5. PLLs
- 2.14.2.1. Ring Oscillator
- 2.14.3. Clock Generators
- 2.14.4. Frequency Counter
- 2.14.5. Resus
- 2.14.6. Programmer’s Model
- 2.14.7. List of registers
- 2.15. Crystal Oscillator (XOSC)
- 2.16. Ring Oscillator (ROSC)
- 2.17. PLL
- 2.18. GPIO
- 2.19. Sysinfo
- 2.20. Syscfg
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. DMA
- 4.3. UART
- 4.4. I2C
- 4.4.1. Features
- 4.4.2. IP Configuration
- 4.4.3. I2C Overview
- 4.4.4. I2C Terminology
- 4.4.5. I2C Behaviour
- 4.4.6. I2C Protocols
- 4.4.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.4.8. Multiple Master Arbitration
- 4.4.9. Clock Synchronization
- 4.4.10. Operation Modes
- 4.4.11. Spike Suppression
- 4.4.12. Fast Mode Plus Operation
- 4.4.13. Bus Clear Feature
- 4.4.14. IC_CLK Frequency Configuration
- 4.4.15. DMA Controller Interface
- 4.4.16. List of Registers
- 4.5. SPI
- 4.5.1. Overview
- 4.5.2. Functional Description
- 4.5.3. Operation
- 4.5.3.1. Interface reset
- 4.5.3.2. Configuring the SSP
- 4.5.3.3. Enable PrimeCell SSP operation
- 4.5.3.4. Clock ratios
- 4.5.3.5. Programming the SSPCR0 Control Register
- 4.5.3.6. Programming the SSPCR1 Control Register
- 4.5.3.7. Frame format
- 4.5.3.8. Texas Instruments synchronous serial frame format
- 4.5.3.9. Motorola SPI frame format
- 4.5.3.10. Motorola SPI Format with SPO=0, SPH=0
- 4.5.3.11. Motorola SPI Format with SPO=0, SPH=1
- 4.5.3.12. Motorola SPI Format with SPO=1, SPH=0
- 4.5.3.13. Motorola SPI Format with SPO=1, SPH=1
- 4.5.3.14. National Semiconductor Microwire frame format
- 4.5.3.15. Examples of master and slave configurations
- 4.5.3.16. PrimeCell DMA interface
- 4.5.4. List of Registers
- 4.6. PWM
- 4.7. Timer
- 4.8. Watchdog
- 4.9. RTC
- 4.10. ADC and Temperature Sensor
- 4.11. SSI
- 4.11.1. Overview
- 4.11.2. Features
- 4.11.3. IP Modifications
- 4.11.4. Clock Ratios
- 4.11.5. Transmit and Receive FIFO Buffers
- 4.11.6. 32-Bit Frame Size Support
- 4.11.7. SSI Interrupts
- 4.11.8. Transfer Modes
- 4.11.9. Operation Modes
- 4.11.10. Partner Connection Interfaces
- 4.11.11. DMA Controller Interface
- 4.11.12. APB Interface
- 4.11.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
control register. Once the buffer control register has been written to, the device controller will respond to the host with the
data. Before this point, the device will reply with a NAK.
Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/usb/device/dev_lowlevel/dev_lowlevel.c Lines 239 - 261
239 void usb_start_transfer(struct usb_endpoint_configuration *ep, uint8_t *buf, uint16_t len)
Ê {
240 // We are asserting that the length is <= 64 bytes for simplicity of the example.
241 // For multi packet transfers see the tinyusb port.
242 assert(len <= 64);
243
244 printf("Start transfer of len %d on ep addr 0x%x\n", len, ep->descriptor-
Ê >bEndpointAddress);
245
246 // Prepare buffer control register value
247 uint32_t val = len | USB_BUF_CTRL_AVAIL;
248
249 if (ep_is_tx(ep)) {
250 // Need to copy the data from the user buffer to the usb memory
251 memcpy((void *) ep->data_buffer, (void *) buf, len);
252 // Mark as full
253 val |= USB_BUF_CTRL_FULL;
254 }
255
256 // Set pid and flip for next transfer
257 val |= ep->next_pid ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID;
258 ep->next_pid ^= 1u;
259
260 *ep->buffer_control = val;
261 }
4.1.4. List of Registers
Table 390. List of USB
registers
Offset Name Info
0x00 ADDR_ENDP Device address and endpoint control
0x04 ADDR_ENDP1 Interrupt endpoint 1. Only valid for HOST mode.
0x08 ADDR_ENDP2 Interrupt endpoint 2. Only valid for HOST mode.
0x0c ADDR_ENDP3 Interrupt endpoint 3. Only valid for HOST mode.
0x10 ADDR_ENDP4 Interrupt endpoint 4. Only valid for HOST mode.
0x14 ADDR_ENDP5 Interrupt endpoint 5. Only valid for HOST mode.
0x18 ADDR_ENDP6 Interrupt endpoint 6. Only valid for HOST mode.
0x1c ADDR_ENDP7 Interrupt endpoint 7. Only valid for HOST mode.
0x20 ADDR_ENDP8 Interrupt endpoint 8. Only valid for HOST mode.
0x24 ADDR_ENDP9 Interrupt endpoint 9. Only valid for HOST mode.
0x28 ADDR_ENDP10 Interrupt endpoint 10. Only valid for HOST mode.
0x2c ADDR_ENDP11 Interrupt endpoint 11. Only valid for HOST mode.
0x30 ADDR_ENDP12 Interrupt endpoint 12. Only valid for HOST mode.
0x34 ADDR_ENDP13 Interrupt endpoint 13. Only valid for HOST mode.
0x38 ADDR_ENDP14 Interrupt endpoint 14. Only valid for HOST mode.
RP2040 Datasheet
4.1. USB 395