Datasheet


WARNING
The USB host controller has a bug (RP2040-E4) that means the status written back to the buffer control register can
appear in the wrong half of the register. Bits 0-15 are for buffer 0, and bits 16-31 are for buffer 1. The host controller
has a buffer selector that is flipped after each transfer is complete. This buffer selector is incorrectly used when
writing status information back to the buffer control register even in single buffered mode. The buffer selector is not
used when reading the buffer control register. The implication of this is that host software needs to keep track of the
buffer selector and shift the buffer control register to the right by 16 bits if the buffer selector is 1.
For more information, see RP2040-E4.
Also see our TinyUSB host code:
https://github.com/raspberrypi/tinyusb/tree/pico/src/portable/raspberrypi/rp2040/rp2040_usb.c Lines 177 - 183.
4.1.2.7.3. OUT
An OUT transfer is triggered with the SEND_TRANS bit set when the START_TRANS bit is set. This may be preceded by a SETUP
packet being sent if the SEND_SETUP bit was set.
CONTROL phase:
•
Read EPx control to get endpoint information (same as Section 4.1.2.7.2)
•
Read EPx buffer control to get the transfer length, data pid. AVAILABLE and FULL must be set for the transfer to start.
TOKEN phase
•
Send OUT packet to the device. The target device address and endpoint come from the ADDR_ENDP register.
DATA phase:
•
Send the first data packet to the device. If the endpoint type is Isochochronous then there is no ACK phase so the
host controller will go straight to status phase. If ACK received then go to status phase. Otherwise:
◦
If no reply is received than raise SIE_STATUS.RX_TIMEOUT.
◦
If NAK received raise SIE_STATUS.NAK_REC and send the data packet again.
◦
If STALL received then raise SIE_STATUS.STALL_REC and go to idle.
STATUS phase:
•
Set BUFF_STATUS bit and update buffer control register. FULL will be set to 0. TRANS_COMPLETE will be set if this is the
last buffer in the transfer.

WARNING
The bug mentioned above (RP2040-E4) in the IN section also applies to the OUT section.
CONTROL phase (pt 2):
If this isn’t the last buffer in the transfer then wait for FULL and AVAILABLE to be set in the EPx buffer control register again.
4.1.2.7.4. Interrupt Endpoints
The host controller can poll interrupt endpoints on many devices (up to a maximum of 15 endpoints). To enable these, the
programmer must:
•
Pick the next free interrupt endpoint slot on the host controller (starting at 1, to a maximum of 15)
•
Program the appropriate endpoint control register and buffer control register like you would with a normal IN or OUT
transfer. Note that interrupt endpoints are only single buffered so the BUF1 part of the buffer control register is invalid.
RP2040 Datasheet
4.1. USB 390