Datasheet

4.1.2.6.1. SETUP
The device controller MUST always accept a setup packet from the host. That is why the first 8 bytes of the DPSRAM has
dedicated space for the setup packet.
The [usbspec] states that receiving a setup packet also clears any stall bits on EP0. For this reason, the stall bits for EP0
are gated with two bits in the EP_STALL_ARM register. These bits are cleared when a setup packet is received. This
means that to send a stall on EP0, you have to set both the stall bit in the buffer control register, and the appropriate bit in
EP_STALL_ARM.
Barring any errors, the setup packet will be put into the setup packet buffer at DPSRAM offset 0x0. The device controller
will then reply with an ACK.
Finally, SIE_STATUS.SETUP_REC is set to indicate that a setup packet has been received. This will trigger an interrupt if
the programmer has enabled the SETUP_REC interrupt (see INTE).
4.1.2.6.2. IN
From the device’s point of view, an IN transfer means transferring data INTO the host. When an IN token is received from
the host the request is handled as follows:
TOKEN phase:
•
If STALL is set in the buffer control register (and if EP0, the appropriate EP_STALL_ARM bit is set) then send a STALL
response and go back to idle.
•
If AVAILABLE and FULL bits are set in buffer control move to the phase
•
Otherwise send NAK unless this is an Isochronous endpoint, in which case go to idle.
DATA phase:
•
Send DATA. If Isochronous go to idle. Otherwise move to ACK phase.
ACK phase:
•
Wait for ACK packet from host. If there is a timeout then raise a timeout error. If ACK is received then the packet is
done, so move to status phase.
STATUS phase:
•
If this was the last buffer in the transfer (i.e. if the LAST_BUFFER bit in the buffer control register was set), set
SIE_STATUS.TRANS_COMPLETE.
•
If the endpoint is double buffered, flip the buffer select to the other buffer.
•
Set a bit in BUFF_STATUS to indicate the buffer is done. When handling this event, the programmer should read
BUFF_CPU_SHOULD_HANDLE to see if it is buffer 0 or buffer 1 that is finished. If the endpoint is double buffered it is
possible to have both buffers done. The cleared BUFF_STATUS bit will be set again, and
BUFF_CPU_SHOULD_HANDLE will change in this instance.
•
Update status in the appropriate half of the buffer control register: length, pid, and last_buff are set. Everything else is
written to zero.
If a NAK gets sent to the host the host will retry again later.
4.1.2.6.3. OUT
When an OUT token is received from the host, the request is handled as follows:
TOKEN phase:
•
Is the DATA pid what is specified in the buffer control register? If not raise SIE_STATUS.DATA_SEQ_ERROR. (The
data pid for an Isochronous endpoint is not checked because Isochronous data is always sent with a DATA0 pid.)
RP2040 Datasheet
4.1. USB 387