Datasheet


NOTE
The data buffer base address must be 64-byte aligned as bits 0-5 are ignored
4.1.2.5.3. Buffer control register
The buffer control register contains information about the state of the data buffers for that endpoint. It is shared between
the processor and the controller. If the endpoint is configured to be single buffered, only the first half (bits 0-15) of the
buffer are used.
If double buffering, the buffer select starts at buffer 0. From then on, the buffer select flips between buffer 0 and 1 unless
the "reset buffer select" bit is set.
For host interrupt and isochronous packets on EPx, the buffer full bit will be set on completion even if the transfer was
unsuccessful. The error bits in the SIE_STATUS register can be read to determine the error.
Table 389. Buffer
control register layout
Bit(s) Function
31 Buffer 1 full - only valid for double buffered
30 Last buffer of transfer for buffer 1 - only valid for double
buffered
29 Data PID for buffer 1 - DATA0 = 0, DATA1 = 1 - only valid for
double buffered
27:28 Double buffer offset for Ichronous mode (0 = 128, 1 = 256,
2 = 512, 3 = 1024)
26 Available - can I be used for a transfer. 1 is yes, 0 is status
from controller
25:16 Transfer length buffer 1 - only valid for double buffered
15 Buffer 0 full
14 Last buffer of transfer for buffer 0
13 Data PID for buffer 0 - DATA0 = 0, DATA1 = 1
12 Reset buffer select to buffer 0 - cleared at end of transfer.
For DEVICE ONLY
11 Send STALL for device, STALL received for host
10 Available - can I be used for a transfer. 1 is yes, 0 is status
from controller
9:0 Transfer length buffer 0

WARNING
If running clk_sys and clk_usb at different speeds, the available and stall bits should be set after the other data in the
buffer control register. Otherwise the controller may initiate a transaction with data from a previous packet. That is to
say, the controller could see the available bit set but get the data pid or length from the previous packet.
4.1.2.6. Device Controller
This section details how the device controller operates when it receives various packet types from the host.
RP2040 Datasheet
4.1. USB 386