Datasheet

Base 0
0
1
MaskAccumulator 0
Result 0
Result 0
Result 1
Result 0
Result 1
Result 2
Accumulator 1
Accumulator 0
Right Shift
Sign-extend
fromMask
Base 2
Base 1
Accumulator 1
0
1
1
0
1
0
1
0
1
0
MaskRight Shift
Sign-extend
fromMask
0
1
0
1
Result 1
+
+
+
Figure 8. An
interpolator. The two
accumulator registers
and three base
registers have single-
cycle read/write
access from the
processor. The
interpolator is
organised into two
lanes, which perform
masking, shifting and
sign-extension
operations on the two
accumulators. This
produces three
possible results, by
adding the
intermediate
shift/mask values to
the three base
registers. From left to
right, the multiplexers
on each lane are
controlled by the
following flags in the
CTRL registers:
CROSS_RESULT,
CROSS_INPUT,
SIGNED, ADD_RAW.
The processor can write or read any interpolator register in one cycle, and the results are ready on the next cycle. The
processor can also perform an addition on one of the two accumulators ACCUM0 or ACCUM1 by writing to the corresponding
ACCUMx_ADD register.
The three results are available in the read-only locations PEEK0, PEEK1, PEEK2. Reading from these locations does not change
the state of the interpolator. The results are also aliased at the locations POP0, POP1, POP2; reading from a POPx alias returns
the same result as the corresponding PEEKx, and simultaneously writes back the lane results to the accumulators. This can
be used to advance the state of interpolator each time a result is read.
Additionally the interpolator supports simple fractional blending between two values as well as clamping values such that
they lie within a given range.
The following example shows a trivial example of popping a lane result to produce simple iterative feedback.
Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/interp/hello_interp/hello_interp.c Lines 11 - 23
11 void times_table() {
12 puts("9 times table:");
13
14 // Initialise lane 0 on interp0 on this core
15 interp_config cfg = interp_default_config();
16 interp_set_config(interp0, 0, &cfg);
17
18 interp0->accum[0] = 0;
19 interp0->base[0] = 9;
20
21 for (int i = 0; i < 10; ++i)
22 printf("%d\n", interp0->pop[0]);
23 }

NOTE
By sheer coincidence, the interpolators are extremely well suited to SNES MODE7-style graphics routines. For example,
on each core, INTERP0 can provide a stream of tile lookups for some affine transform, and INTERP1 can provide
offsets into the tiles for the same transform.
2.3.1.6.1. Lane Operations
RP2040 Datasheet
2.3. Processor subsystem 37