Datasheet

Bits Name Description Type Reset
18 IN_SHIFTDIR 1 = shift input shift register to right (data enters from left). 0
= to left.
RW 0x1
17 AUTOPULL Pull automatically when the output shift register is emptied RW 0x0
16 AUTOPUSH Push automatically when the input shift register is filled RW 0x0
15:0 Reserved. - - -
SM0_ADDR, SM1_ADDR, SM2_ADDR, SM3_ADDR Registers
Description
Current instruction address of state machine N
Table 377. SM0_ADDR,
SM1_ADDR,
SM2_ADDR,
SM3_ADDR Registers
Bits Name Description Type Reset
31:5 Reserved. - - -
4:0 NONAME RO 0x00
SM0_INSTR, SM1_INSTR, SM2_INSTR, SM3_INSTR Registers
Description
Instruction currently being executed by state machine N.
Write to execute an instruction immediately (including jumps) and then resume execution.
Table 378.
SM0_INSTR,
SM1_INSTR,
SM2_INSTR,
SM3_INSTR Registers
Bits Name Description Type Reset
31:16 Reserved. - - -
15:0 NONAME RW -
SM0_PINCTRL, SM1_PINCTRL, SM2_PINCTRL, SM3_PINCTRL Registers
Table 379.
SM0_PINCTRL,
SM1_PINCTRL,
SM2_PINCTRL,
SM3_PINCTRL
Registers
Bits Name Description Type Reset
31:29 SIDESET_COUNT The number of delay bits co-opted for side-set. Inclusive of
the enable bit, if present.
RW 0x0
28:26 SET_COUNT The number of pins asserted by a SET. Max of 5 RW 0x5
25:20 OUT_COUNT The number of pins asserted by an OUT. Value of 0 -> 32
pins
RW 0x00
19:15 IN_BASE The virtual pin corresponding to IN bit 0 RW 0x00
14:10 SIDESET_BASE The virtual pin corresponding to delay field bit 0 RW 0x00
9:5 SET_BASE The virtual pin corresponding to SET bit 0 RW 0x00
4:0 OUT_BASE The virtual pin corresponding to OUT bit 0 RW 0x00
INTR Register
Description
Raw Interrupts
Table 380. INTR
Register
Bits Name Description Type Reset
31:12 Reserved. - - -
RP2040 Datasheet
3.8. List of Registers 376