Datasheet

Bits Name Description Type Reset
28:24 JMP_PIN The GPIO number to use as condition for JMP PIN.
Unaffected by input mapping.
RW 0x00
23:19 OUT_EN_SEL Which data bit to use for inline OUT enable RW 0x00
18 INLINE_OUT_EN If 1, use a bit of OUT data as an auxiliary write enable
When used in conjunction with OUT_STICKY, writes with an
enable of 0 will
deassert the latest pin write. This can create useful
masking/override behaviour
due to the priority ordering of state machine pin writes
(SM0 < SM1 < …)
RW 0x0
17 OUT_STICKY Continuously assert the most recent OUT/SET to the pins RW 0x0
16:12 WRAP_TOP After reaching this address, execution is wrapped to
wrap_bottom.
If the instruction is a jump, and the jump condition is true,
the jump takes priority.
RW 0x1f
11:7 WRAP_BOTTOM After reaching wrap_top, execution is wrapped to this
address.
RW 0x00
6:5 Reserved. - - -
4 STATUS_SEL Comparison used for the MOV x, STATUS instruction.
0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes
0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes
RW 0x0
3:0 STATUS_N Comparison level for the MOV x, STATUS instruction RW 0x0
SM0_SHIFTCTRL, SM1_SHIFTCTRL, SM2_SHIFTCTRL, SM3_SHIFTCTRL
Registers
Description
Control behaviour of the input/output shift registers for state machine N
Table 376.
SM0_SHIFTCTRL,
SM1_SHIFTCTRL,
SM2_SHIFTCTRL,
SM3_SHIFTCTRL
Registers
Bits Name Description Type Reset
31 FJOIN_RX When 1, RX FIFO steals the TX FIFO’s storage, and
becomes twice as deep.
TX FIFO is disabled as a result (always reads as both full
and empty).
FIFOs are flushed when this bit is changed.
RW 0x0
30 FJOIN_TX When 1, TX FIFO steals the RX FIFO’s storage, and
becomes twice as deep.
RX FIFO is disabled as a result (always reads as both full
and empty).
FIFOs are flushed when this bit is changed.
RW 0x0
29:25 PULL_THRESH Number of bits shifted out of TXSR before autopull or
conditional pull.
Write 0 for value of 32.
RW 0x00
24:20 PUSH_THRESH Number of bits shifted into RXSR before autopush or
conditional push.
Write 0 for value of 32.
RW 0x00
19 OUT_SHIFTDIR 1 = shift out of output shift register to right. 0 = to left. RW 0x1
RP2040 Datasheet
3.8. List of Registers 375