Datasheet

Bits Name Description Type Reset
21:16 IMEM_SIZE The size of the instruction memory, measured in units of
one instruction
RO -
15:12 Reserved. - - -
11:8 SM_COUNT The number of state machines this PIO instance is
equipped with.
RO -
7:6 Reserved. - - -
5:0 FIFO_DEPTH The depth of the state machine TX/RX FIFOs, measured in
words.
Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with
double
this depth.
RO -
INSTR_MEM0, INSTR_MEM1, …, INSTR_MEM30, INSTR_MEM31 Registers
Table 373.
INSTR_MEM0,
INSTR_MEM1, …,
INSTR_MEM30,
INSTR_MEM31
Registers
Bits Name Description Type Reset
31:16 Reserved. - - -
15:0 NONAME Write-only access to instruction memory location N WO 0x0000
SM0_CLKDIV, SM1_CLKDIV, SM2_CLKDIV, SM3_CLKDIV Registers
Description
Clock divider register for state machine N
Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
Table 374.
SM0_CLKDIV,
SM1_CLKDIV,
SM2_CLKDIV,
SM3_CLKDIV
Registers
Bits Name Description Type Reset
31:16 INT Effective frequency is sysclk/int.
Value of 0 is interpreted as max possible value
RW 0x0001
15:8 FRAC Fractional part of clock divider RW 0x00
7:0 Reserved. - - -
SM0_EXECCTRL, SM1_EXECCTRL, SM2_EXECCTRL, SM3_EXECCTRL
Registers
Description
Execution/behavioural settings for state machine N
Table 375.
SM0_EXECCTRL,
SM1_EXECCTRL,
SM2_EXECCTRL,
SM3_EXECCTRL
Registers
Bits Name Description Type Reset
31 EXEC_STALLED An instruction written to SMx_INSTR is stalled, and latched
by the
state machine. Will clear once the instruction completes.
RO 0x0
30 SIDE_EN If 1, the delay MSB is used as side-set enable, rather than a
side-set data bit. This allows instructions to perform side-
set optionally,
rather than on every instruction.
RW 0x0
29 SIDE_PINDIR Side-set data is asserted to pin OEs instead of pin values RW 0x0
RP2040 Datasheet
3.8. List of Registers 374