Datasheet

3.8. List of Registers
Table 360. List of PIO
registers
Offset Name Info
0x000 CTRL PIO control register
0x004 FSTAT FIFO status register
0x008 FDEBUG FIFO debug register
0x00c FLEVEL FIFO levels
0x010 TXF0 Direct write access to the TX FIFO for this state machine. Each
write pushes one word to the FIFO.
0x014 TXF1 Direct write access to the TX FIFO for this state machine. Each
write pushes one word to the FIFO.
0x018 TXF2 Direct write access to the TX FIFO for this state machine. Each
write pushes one word to the FIFO.
0x01c TXF3 Direct write access to the TX FIFO for this state machine. Each
write pushes one word to the FIFO.
0x020 RXF0 Direct read access to the RX FIFO for this state machine. Each
read pops one word from the FIFO.
0x024 RXF1 Direct read access to the RX FIFO for this state machine. Each
read pops one word from the FIFO.
0x028 RXF2 Direct read access to the RX FIFO for this state machine. Each
read pops one word from the FIFO.
0x02c RXF3 Direct read access to the RX FIFO for this state machine. Each
read pops one word from the FIFO.
0x030 IRQ Interrupt request register. Write 1 to clear
0x034 IRQ_FORCE Writing a 1 to each of these bits will forcibly assert the
corresponding IRQ.
Note this is different to the INTF register: writing here affects PIO
internal
state. INTF just asserts the processor-facing IRQ signal for testing
ISRs,
and is not visible to the state machines.
0x038 INPUT_SYNC_BYPASS There is a 2-flipflop synchronizer on each GPIO input, which
protects
PIO logic from metastabilities. This increases input delay, and for
fast
synchronous IO (e.g. SPI) these synchronizers may need to be
bypassed.
Each bit in this register corresponds to one GPIO.
0 -> input is synchronized (default)
1 -> synchronizer is bypassed
If in doubt, leave this register as all zeroes.
0x03c DBG_PADOUT
0x040 DBG_PADOE
RP2040 Datasheet
3.8. List of Registers 368