Datasheet

Ê4 ; | high len | low len | (dither, continue) * n |
Ê5
Ê6 start:
Ê7 out y, 7 ; Stash the two base pulse lengths
Ê8 mov isr, y ; (ab)use ISR as 3rd scratch register
Ê9 out y, 7
10 .wrap_target
11 out pins, 1 ; Dither is prepended to next 1, or appended to prev 0
12 mov x, isr side 1
13 loop1:
14 jmp x-- loop1
15 mov x, y side 0
16 loop0:
17 jmp x-- loop0
18 out x, 1
19 jmp !x start ; Branch on continue bit
20 nop [2] ; Ensure carrier freq is constant
21 .wrap
Alternatively, if variable length is not required, the "output shift register not empty" condition can be used. This allows
twice as many dithering bits to be packed into the FIFO words. The number of dithering bits is still configurable by setting
the autopull threshold. Note that, in this case, autopull must be disabled, since the refilling of the OSR will affect 'jmp
!osre'.
Ê1 .side_set 1 opt
Ê2
Ê3 ; FIFO Format:
Ê4 ; | high len | low len | dither * n |
Ê5
Ê6 start:
Ê7 pull
Ê8 out y, 7 ; Stash the two base pulse lengths
Ê9 mov isr, y ; (ab)use ISR as 3rd scratch register
10 out y, 7
11 .wrap_target
12 out pins, 1 ; Dither is prepended to next 1, or appended to prev 0
13 mov x, isr side 1
14 loop1:
15 jmp x-- loop1
16 mov x, y side 0
17 loop0:
18 jmp x-- loop0
19 jmp !osre start
20 nop [2] ; Ensure carrier freq is constant
21 .wrap
3.7.3. I2C
Ê1 ; TX Encoding:
Ê2 ; | 15:10 | 9 | 8:1 | 0 |
Ê3 ; | Instr | Final | Data | NAK |
Ê4 ;
Ê5 ; If Instr has a value n > 0, then this FIFO word has no
Ê6 ; data payload, and the next n + 1 words will be executed as instructions.
Ê7 ; Otherwise, shift out the 8 data bits, followed by the ACK bit.
Ê8 ;
RP2040 Datasheet
3.7. Outdated Examples 364