Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.4.1. Features
- 2.4.2. Functional Description
- 2.4.3. Programmer’s model
- 2.4.4. System control
- 2.4.5. NVIC
- 2.4.6. MPU
- 2.4.7. Debug
- 2.4.8. List of Registers
- 2.5. Memory
- 2.6. Boot Sequence
- 2.7. Bootrom
- 2.7.1. Bootrom Source
- 2.7.2. Processor Controlled Boot Sequence
- 2.7.3. Bootrom Contents
- 2.7.4. USB Mass Storage Interface
- 2.7.5. USB PICOBOOT Interface
- 2.8. Power Supplies
- 2.9. On-Chip Voltage Regulator
- 2.10. Power Control
- 2.11. Chip-Level Reset
- 2.12. Power-On State Machine
- 2.13. Subsystem Resets
- 2.14. Clocks
- 2.14.1. Overview
- 2.14.2. Clock sources
- 2.14.2.1. Ring Oscillator
- 2.14.2.1.1. Mitigating ROSC frequency variation due to process
- 2.14.2.1.2. Mitigating ROSC frequency variation due to voltage
- 2.14.2.1.3. Mitigating ROSC frequency variation due to temperature
- 2.14.2.1.4. Automatic mitigation of ROSC frequency variation due to PVT
- 2.14.2.1.5. Automatic overclocking using the ROSC
- 2.14.2.2. Crystal Oscillator
- 2.14.2.3. External Clocks
- 2.14.2.4. Relaxation Oscillators
- 2.14.2.5. PLLs
- 2.14.2.1. Ring Oscillator
- 2.14.3. Clock Generators
- 2.14.4. Frequency Counter
- 2.14.5. Resus
- 2.14.6. Programmer’s Model
- 2.14.7. List of registers
- 2.15. Crystal Oscillator (XOSC)
- 2.16. Ring Oscillator (ROSC)
- 2.17. PLL
- 2.18. GPIO
- 2.19. Sysinfo
- 2.20. Syscfg
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. DMA
- 4.3. UART
- 4.4. I2C
- 4.4.1. Features
- 4.4.2. IP Configuration
- 4.4.3. I2C Overview
- 4.4.4. I2C Terminology
- 4.4.5. I2C Behaviour
- 4.4.6. I2C Protocols
- 4.4.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.4.8. Multiple Master Arbitration
- 4.4.9. Clock Synchronization
- 4.4.10. Operation Modes
- 4.4.11. Spike Suppression
- 4.4.12. Fast Mode Plus Operation
- 4.4.13. Bus Clear Feature
- 4.4.14. IC_CLK Frequency Configuration
- 4.4.15. DMA Controller Interface
- 4.4.16. List of Registers
- 4.5. SPI
- 4.5.1. Overview
- 4.5.2. Functional Description
- 4.5.3. Operation
- 4.5.3.1. Interface reset
- 4.5.3.2. Configuring the SSP
- 4.5.3.3. Enable PrimeCell SSP operation
- 4.5.3.4. Clock ratios
- 4.5.3.5. Programming the SSPCR0 Control Register
- 4.5.3.6. Programming the SSPCR1 Control Register
- 4.5.3.7. Frame format
- 4.5.3.8. Texas Instruments synchronous serial frame format
- 4.5.3.9. Motorola SPI frame format
- 4.5.3.10. Motorola SPI Format with SPO=0, SPH=0
- 4.5.3.11. Motorola SPI Format with SPO=0, SPH=1
- 4.5.3.12. Motorola SPI Format with SPO=1, SPH=0
- 4.5.3.13. Motorola SPI Format with SPO=1, SPH=1
- 4.5.3.14. National Semiconductor Microwire frame format
- 4.5.3.15. Examples of master and slave configurations
- 4.5.3.16. PrimeCell DMA interface
- 4.5.4. List of Registers
- 4.6. PWM
- 4.7. Timer
- 4.8. Watchdog
- 4.9. RTC
- 4.10. ADC and Temperature Sensor
- 4.11. SSI
- 4.11.1. Overview
- 4.11.2. Features
- 4.11.3. IP Modifications
- 4.11.4. Clock Ratios
- 4.11.5. Transmit and Receive FIFO Buffers
- 4.11.6. 32-Bit Frame Size Support
- 4.11.7. SSI Interrupts
- 4.11.8. Transfer Modes
- 4.11.9. Operation Modes
- 4.11.10. Partner Connection Interfaces
- 4.11.11. DMA Controller Interface
- 4.11.12. APB Interface
- 4.11.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
20 jmp !x high_0 [6] ; Test the data bit we just shifted out of OSR
21 high_1:
22 jmp initial_high side 0 [7] ; For `1` bits, also transition in the middle
23 high_0:
24 jmp initial_low [7] ; Otherwise, the line is stable in the middle
25
26 initial_low:
27 out x, 1 side 0 ; Always shift 1 bit from OSR to X so we can
28 jmp !x low_0 [6] ; branch on it. Autopull refills OSR for us.
29 low_1:
30 jmp initial_low side 1 [7] ; If there are two transitions, return to
31 low_0: ; initial_low on the next bit. If just one,
32 jmp initial_high [7] ; the initial line state is flipped!
The .pio file also includes a helper function to initialise a state machine for differential Manchester TX, and connect it to a
chosen GPIO. We arbitrarily choose a 32-bit frame size and LSB-first serialisation (shift_to_right is true in
sm_config_set_out_shift), but as the program operates on one bit at a time, we could change this by reconfiguring the state
machine.
Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/pio/differential_manchester/differential_manchester.pio Lines 35 - 50
35 static inline void differential_manchester_tx_program_init(PIO pio, uint sm, uint offset,
Ê uint pin, float div) {
36 pio_sm_set_pins_with_mask(pio, sm, 0, 1u << pin);
37 pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, true);
38 pio_gpio_select(pio, pin);
39
40 pio_sm_config c = differential_manchester_tx_program_get_default_config(offset);
41 sm_config_set_sideset_pins(&c, pin);
42 sm_config_set_out_shift(&c, true, true, 32);
43 sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
44 sm_config_set_clkdiv(&c, div);
45 pio_sm_init(pio, sm, offset + differential_manchester_tx_offset_start, &c);
46
47 // Execute a blocking pull so that we maintain the initial line state until data is
Ê available
48 pio_sm_exec(pio, sm, pio_encode_pull(false, true));
49 pio_sm_enable(pio, sm, true);
50 }
The RX program uses the following strategy:
•
Wait until the initial transition at the start of the bit period, so we stay aligned to the transmit clock
•
Then wait 3/4 of the configured bit period, so that we are centred on the second half-bit-period (see Figure 52)
•
Sample the line at this point to determine whether there are one or two transitions in this bit period
•
Repeat
Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/pio/differential_manchester/differential_manchester.pio Lines 52 - 82
52 .program differential_manchester_rx
53
54 ; Assumes line is idle low
55 ; One bit is 16 cycles. In each bit period:
56 ; - A '0' is encoded as a transition at time 0
57 ; - A '1' is encoded as a transition at time 0 and a transition at time T/2
58 ;
59 ; The IN mapping and the JMP pin select must both be mapped to the GPIO used for
60 ; RX data. Autopush must be enabled.
RP2040 Datasheet
3.6. Examples 358