Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.4.1. Features
- 2.4.2. Functional Description
- 2.4.3. Programmer’s model
- 2.4.4. System control
- 2.4.5. NVIC
- 2.4.6. MPU
- 2.4.7. Debug
- 2.4.8. List of Registers
- 2.5. Memory
- 2.6. Boot Sequence
- 2.7. Bootrom
- 2.7.1. Bootrom Source
- 2.7.2. Processor Controlled Boot Sequence
- 2.7.3. Bootrom Contents
- 2.7.4. USB Mass Storage Interface
- 2.7.5. USB PICOBOOT Interface
- 2.8. Power Supplies
- 2.9. On-Chip Voltage Regulator
- 2.10. Power Control
- 2.11. Chip-Level Reset
- 2.12. Power-On State Machine
- 2.13. Subsystem Resets
- 2.14. Clocks
- 2.14.1. Overview
- 2.14.2. Clock sources
- 2.14.2.1. Ring Oscillator
- 2.14.2.1.1. Mitigating ROSC frequency variation due to process
- 2.14.2.1.2. Mitigating ROSC frequency variation due to voltage
- 2.14.2.1.3. Mitigating ROSC frequency variation due to temperature
- 2.14.2.1.4. Automatic mitigation of ROSC frequency variation due to PVT
- 2.14.2.1.5. Automatic overclocking using the ROSC
- 2.14.2.2. Crystal Oscillator
- 2.14.2.3. External Clocks
- 2.14.2.4. Relaxation Oscillators
- 2.14.2.5. PLLs
- 2.14.2.1. Ring Oscillator
- 2.14.3. Clock Generators
- 2.14.4. Frequency Counter
- 2.14.5. Resus
- 2.14.6. Programmer’s Model
- 2.14.7. List of registers
- 2.15. Crystal Oscillator (XOSC)
- 2.16. Ring Oscillator (ROSC)
- 2.17. PLL
- 2.18. GPIO
- 2.19. Sysinfo
- 2.20. Syscfg
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. DMA
- 4.3. UART
- 4.4. I2C
- 4.4.1. Features
- 4.4.2. IP Configuration
- 4.4.3. I2C Overview
- 4.4.4. I2C Terminology
- 4.4.5. I2C Behaviour
- 4.4.6. I2C Protocols
- 4.4.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.4.8. Multiple Master Arbitration
- 4.4.9. Clock Synchronization
- 4.4.10. Operation Modes
- 4.4.11. Spike Suppression
- 4.4.12. Fast Mode Plus Operation
- 4.4.13. Bus Clear Feature
- 4.4.14. IC_CLK Frequency Configuration
- 4.4.15. DMA Controller Interface
- 4.4.16. List of Registers
- 4.5. SPI
- 4.5.1. Overview
- 4.5.2. Functional Description
- 4.5.3. Operation
- 4.5.3.1. Interface reset
- 4.5.3.2. Configuring the SSP
- 4.5.3.3. Enable PrimeCell SSP operation
- 4.5.3.4. Clock ratios
- 4.5.3.5. Programming the SSPCR0 Control Register
- 4.5.3.6. Programming the SSPCR1 Control Register
- 4.5.3.7. Frame format
- 4.5.3.8. Texas Instruments synchronous serial frame format
- 4.5.3.9. Motorola SPI frame format
- 4.5.3.10. Motorola SPI Format with SPO=0, SPH=0
- 4.5.3.11. Motorola SPI Format with SPO=0, SPH=1
- 4.5.3.12. Motorola SPI Format with SPO=1, SPH=0
- 4.5.3.13. Motorola SPI Format with SPO=1, SPH=1
- 4.5.3.14. National Semiconductor Microwire frame format
- 4.5.3.15. Examples of master and slave configurations
- 4.5.3.16. PrimeCell DMA interface
- 4.5.4. List of Registers
- 4.6. PWM
- 4.7. Timer
- 4.8. Watchdog
- 4.9. RTC
- 4.10. ADC and Temperature Sensor
- 4.11. SSI
- 4.11.1. Overview
- 4.11.2. Features
- 4.11.3. IP Modifications
- 4.11.4. Clock Ratios
- 4.11.5. Transmit and Receive FIFO Buffers
- 4.11.6. 32-Bit Frame Size Support
- 4.11.7. SSI Interrupts
- 4.11.8. Transfer Modes
- 4.11.9. Operation Modes
- 4.11.10. Partner Connection Interfaces
- 4.11.11. DMA Controller Interface
- 4.11.12. APB Interface
- 4.11.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/pio/manchester_encoding/manchester_encoding.pio Lines 48 - 70
48 .program manchester_rx
49
50 ; Assumes line is idle low, first bit is 0
51 ; One bit is 12 cycles
52 ; a '0' is encoded as 10
53 ; a '1' is encoded as 01
54 ;
55 ; Both the IN base and the JMP pin mapping must be pointed at the GPIO used for RX.
56 ; Autopush must be enabled.
57 ; Before enabling the SM, it should be placed in a 'wait 1, pin` state, so that
58 ; it will not start sampling until the initial line idle state ends.
59
60 start_of_0: ; We are 0.25 bits into a 0 - signal is high
61 wait 0 pin 0 ; Wait for the 1->0 transition - at this point we are 0.5 into the
Ê bit
62 in y, 1 [8] ; Emit a 0, sleep 3/4 of a bit
63 jmp pin start_of_0 ; If signal is 1 again, it's another 0 bit, otherwise it's a 1
64
65 .wrap_target
66 start_of_1: ; We are 0.25 bits into a 1 - signal is 1
67 wait 1 pin 0 ; Wait for the 0->1 transition - at this point we are 0.5 into the
Ê bit
68 in x, 1 [8] ; Emit a 1, sleep 3/4 of a bit
69 jmp pin start_of_0 ; If signal is 0 again, it's another 1 bit otherwise it's a 0
70 .wrap
The main complication here is staying aligned to the input transitions, as the transmitter’s and receiver’s clocks may drift
relative to one another. In Manchester code there is always a transition in the centre of the symbol, and based on the
initial line state (high or low) we know the direction of this transition, so we can use a wait instruction to resynchronise to
the line transitions on every data bit.
This program expects the X and Y registers to be initialised with the values 1 and 0 respectively, so that a constant 1 or 0
can be provided to the in instruction. The code that configures the state machine initialises these registers by executing
some set instructions before setting the program running.
Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/pio/manchester_encoding/manchester_encoding.pio Lines 73 - 93
73 static inline void manchester_rx_program_init(PIO pio, uint sm, uint offset, uint pin, float
Ê div) {
74 pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, false);
75 pio_gpio_select(pio, pin);
76
77 pio_sm_config c = manchester_rx_program_get_default_config(offset);
78 sm_config_set_in_pins(&c, pin); // for WAIT
79 sm_config_set_jmp_pin(&c, pin); // for JMP
80 sm_config_set_in_shift(&c, true, true, 32);
81 sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
82 sm_config_set_clkdiv(&c, div);
83 pio_sm_init(pio, sm, offset, &c);
84
85 // X and Y are set to 0 and 1, to conveniently emit these to ISR/FIFO.
86 pio_sm_exec(pio, sm, pio_encode_set(pio_x, 1));
87 pio_sm_exec(pio, sm, pio_encode_set(pio_y, 0));
88 // Assume line is idle low, and first transmitted bit is 0. Put SM in a
89 // wait state before enabling. RX will begin once the first 0 symbol is
90 // detected.
91 pio_sm_exec(pio, sm, pio_encode_wait_pin(1, 0) | pio_encode_delay(2));
92 pio_sm_enable(pio, sm, true);
93 }
RP2040 Datasheet
3.6. Examples 356