Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.4.1. Features
- 2.4.2. Functional Description
- 2.4.3. Programmer’s model
- 2.4.4. System control
- 2.4.5. NVIC
- 2.4.6. MPU
- 2.4.7. Debug
- 2.4.8. List of Registers
- 2.5. Memory
- 2.6. Boot Sequence
- 2.7. Bootrom
- 2.7.1. Bootrom Source
- 2.7.2. Processor Controlled Boot Sequence
- 2.7.3. Bootrom Contents
- 2.7.4. USB Mass Storage Interface
- 2.7.5. USB PICOBOOT Interface
- 2.8. Power Supplies
- 2.9. On-Chip Voltage Regulator
- 2.10. Power Control
- 2.11. Chip-Level Reset
- 2.12. Power-On State Machine
- 2.13. Subsystem Resets
- 2.14. Clocks
- 2.14.1. Overview
- 2.14.2. Clock sources
- 2.14.2.1. Ring Oscillator
- 2.14.2.1.1. Mitigating ROSC frequency variation due to process
- 2.14.2.1.2. Mitigating ROSC frequency variation due to voltage
- 2.14.2.1.3. Mitigating ROSC frequency variation due to temperature
- 2.14.2.1.4. Automatic mitigation of ROSC frequency variation due to PVT
- 2.14.2.1.5. Automatic overclocking using the ROSC
- 2.14.2.2. Crystal Oscillator
- 2.14.2.3. External Clocks
- 2.14.2.4. Relaxation Oscillators
- 2.14.2.5. PLLs
- 2.14.2.1. Ring Oscillator
- 2.14.3. Clock Generators
- 2.14.4. Frequency Counter
- 2.14.5. Resus
- 2.14.6. Programmer’s Model
- 2.14.7. List of registers
- 2.15. Crystal Oscillator (XOSC)
- 2.16. Ring Oscillator (ROSC)
- 2.17. PLL
- 2.18. GPIO
- 2.19. Sysinfo
- 2.20. Syscfg
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. DMA
- 4.3. UART
- 4.4. I2C
- 4.4.1. Features
- 4.4.2. IP Configuration
- 4.4.3. I2C Overview
- 4.4.4. I2C Terminology
- 4.4.5. I2C Behaviour
- 4.4.6. I2C Protocols
- 4.4.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.4.8. Multiple Master Arbitration
- 4.4.9. Clock Synchronization
- 4.4.10. Operation Modes
- 4.4.11. Spike Suppression
- 4.4.12. Fast Mode Plus Operation
- 4.4.13. Bus Clear Feature
- 4.4.14. IC_CLK Frequency Configuration
- 4.4.15. DMA Controller Interface
- 4.4.16. List of Registers
- 4.5. SPI
- 4.5.1. Overview
- 4.5.2. Functional Description
- 4.5.3. Operation
- 4.5.3.1. Interface reset
- 4.5.3.2. Configuring the SSP
- 4.5.3.3. Enable PrimeCell SSP operation
- 4.5.3.4. Clock ratios
- 4.5.3.5. Programming the SSPCR0 Control Register
- 4.5.3.6. Programming the SSPCR1 Control Register
- 4.5.3.7. Frame format
- 4.5.3.8. Texas Instruments synchronous serial frame format
- 4.5.3.9. Motorola SPI frame format
- 4.5.3.10. Motorola SPI Format with SPO=0, SPH=0
- 4.5.3.11. Motorola SPI Format with SPO=0, SPH=1
- 4.5.3.12. Motorola SPI Format with SPO=1, SPH=0
- 4.5.3.13. Motorola SPI Format with SPO=1, SPH=1
- 4.5.3.14. National Semiconductor Microwire frame format
- 4.5.3.15. Examples of master and slave configurations
- 4.5.3.16. PrimeCell DMA interface
- 4.5.4. List of Registers
- 4.6. PWM
- 4.7. Timer
- 4.8. Watchdog
- 4.9. RTC
- 4.10. ADC and Temperature Sensor
- 4.11. SSI
- 4.11.1. Overview
- 4.11.2. Features
- 4.11.3. IP Modifications
- 4.11.4. Clock Ratios
- 4.11.5. Transmit and Receive FIFO Buffers
- 4.11.6. 32-Bit Frame Size Support
- 4.11.7. SSI Interrupts
- 4.11.8. Transfer Modes
- 4.11.9. Operation Modes
- 4.11.10. Partner Connection Interfaces
- 4.11.11. DMA Controller Interface
- 4.11.12. APB Interface
- 4.11.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
3.6.3. UART TX
Bit Clock
TX
State
10 2 3 4 5 6 7
Start StopData (LSB first)Idle
Figure 50. UART serial
format. The line is
high when idle. The
transmitter pulls the
line down for one bit
period to signify the
start of a serial frame
(the "start bit"), and a
small, fixed number of
data bits follows. The
line returns to the idle
state for at least one
bit period (the "stop
bit") before the next
serial frame can
begin.
This program implements the transmit component of a universal asynchronous receive/transmit (UART) serial peripheral.
Perhaps it would be more correct to refer to this as a UAT.
Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/pio/uart_tx/uart_tx.pio Lines 7 - 17
Ê7 .program uart_tx
Ê8 .side_set 1 opt
Ê9
10 ; An 8n1 UART transmit program.
11 ; OUT pin 0 and side-set pin 0 are both mapped to UART TX pin.
12
13 pull side 1 [7] ; Assert stop bit, or stall with line in idle state
14 set x, 7 side 0 [7] ; Preload bit counter, assert start bit for 8 clocks
15 bitloop: ; This loop will run 8 times (8n1 UART)
16 out pins, 1 ; Shift 1 bit from OSR to the first OUT pin
17 jmp x-- bitloop [6] ; Each loop iteration is 8 cycles.
As written, it will:
•
Stall with the pin driven high until data appears (noting that side-set takes effect even when the state machine is
stalled)
•
Assert a start bit, for 8 SM execution cycles
•
Shift out 8 data bits, each lasting for 8 cycles
•
Return to the idle line state for at least 8 cycles before asserting the next start bit
If the state machine’s clock divider is configured to run at 8 times the desired baud rate, this program will transmit well-
formed UART serial frames, whenever data is pushed to the TX FIFO either by software or the system DMA. To extend the
program to cover different frame sizes (different numbers of data bits), the set x, 7 could be replaced with mov x, y, so
that the y scratch register becomes a per-SM configuration register for UART frame size.
The .pio file in the SDK also contains this function, for configuring the pins and the state machine, once the program has
been loaded into the PIO instruction memory:
Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/pio/uart_tx/uart_tx.pio Lines 23 - 50
23 static inline void uart_tx_program_init(PIO pio, uint sm, uint offset, uint pin_tx, uint
Ê baud) {
24 // Tell PIO to initially drive output-high on the selected pin, then map PIO
25 // onto that pin with the IO muxes.
26 pio_sm_set_pins_with_mask(pio, sm, 1u << pin_tx, 1u << pin_tx);
27 pio_sm_set_pindirs_with_mask(pio, sm, 1u << pin_tx, 1u << pin_tx);
28 pio_gpio_select(pio, pin_tx);
29
30 pio_sm_config c = uart_tx_program_get_default_config(offset);
31
32 // OUT shifts to right, no autopull
33 sm_config_set_out_shift(&c, true, false, 32);
34
35 // We are mapping both OUT and side-set to the same pin, because sometimes
36 // we need to assert user data onto the pin (with OUT) and sometimes
37 // assert constant values (start/stop bit)
38 sm_config_set_out_pins(&c, pin_tx, 1);
RP2040 Datasheet
3.6. Examples 350