Datasheet

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NOTE
This is a conceptual model for the result that is produced when two cores write to a GPIO register simultaneously. The
register does not actually contain this intermediate value at any point. In the previous example, if the pin is initially 0,
and core 0 performs a SET while core 1 performs a XOR, the GPIO output remains low without any positive glitch.
2.3.1.3. Hardware Spinlocks
The SIO provides 32 hardware spinlocks, which can be used to manage mutually-exclusive access to shared software
resources. Each spinlock is a one-bit flag, mapped to a different address (from SPINLOCK0 to SPINLOCK31). Software
interacts with each spinlock with one of the following operations:
•
Read: attempt to claim the lock. Read value is nonzero if the lock was successfully claimed, or zero if the lock had
already been claimed by a previous read.
•
Write (any value): release the lock. The next attempt to claim the lock will be successful.
If both cores try to claim the same lock on the same clock cycle, core 0 succeeds.
Generally software will acquire a lock by repeatedly polling the lock bit ("spinning" on the lock) until it is successfully
claimed. This is inefficient if the lock is held for long periods, so generally the spinlocks should be used to protect the
short critical sections of higher-level primitives such as mutexes, semaphores and queues.
For debugging purposes, the current state of all 32 spinlocks can be observed via SPINLOCK_ST.
2.3.1.4. Inter-processor FIFOs (Mailboxes)
The SIO contains two FIFOs for passing data, messages or ordered events between the two cores. Each FIFO is 32 bits
wide, and eight entries deep. One of the FIFOs can only be written by core 0, and read by core 1. The other can only be
written by core 1, and read by core 0.
Each core writes to its outgoing FIFO by writing to FIFO_WR, and reads from its incoming FIFO by reading from FIFO_RD.
A status register, FIFO_ST, provides the following status signals:
•
Incoming FIFO contains data (VLD)
•
Outgoing FIFO has room for more data (RDY)
•
The incoming FIFO was read from while empty at some point in the past (ROE)
•
The outgoing FIFO was written to while full at some point in the past (WOF)
Writing to the outgoing FIFO while full, or reading from the incoming FIFO while empty, does not affect the FIFO state. The
current contents and level of the FIFO is preserved. However, this does represent some loss of data or reception of invalid
data by the software accessing the FIFO, so a sticky error flag is raised (ROE or WOF).
The SIO has a FIFO IRQ output for each core, mapped to system IRQ numbers 15 and 16. The IRQ is asserted when any of
VLD, ROE or WOF is 1 in that core’s FIFO_ST register. If the corresponding interrupt line is enabled in the Cortex-M0+ NVIC,
then the processor will take an interrupt each time data appears in its FIFO, or if it has performed some invalid FIFO
operation (read on empty, write on full). Typically Core 0 will use IRQ15 and core 1 will use IRQ16. If the IRQs are used the
other way round then it is difficult for the core that has been interrupted to correctly identify the reason for the interrupt as
the core doesn’t have access to the other core’s FIFO status register.
The interrupt handler acknowledges the ROE and WOF flags by writing any value to FIFO_ST. The VLD flag is cleared by
reading data from the FIFO until empty.
The inter-processor FIFOs and the Cortex-M0+ Event signals are used by the Bootrom wait_for_vector routine, where core
1 remains in a sleep state until it is woken, and provided with its initial stack pointer, entry point and vector table through
the FIFO.
RP2040 Datasheet
2.3. Processor subsystem 34