Datasheet

System Clock
CLKDIV_INT
CLKDIV_FRAC
Clock Enable
CTRL_SM_ENABLE
2
.5
Figure 45. Fractional
clock division with an
average divisor of 2.5.
The clock divider
maintains a running
total of the fractional
value from each
division period, and
every time this value
wraps through 1, the
integer divisor is
increased by one for
the next division
period.
For small n, the jitter introduced by a fractional divider may be unacceptable. However, for larger values, this effect is
much less apparent.

NOTE
For fast asynchronous serial, it is recommended to use even divisions or multiples of 1 Mbaud where possible, rather
than the traditional multiples of 300, to avoid unnecessary jitter.
3.5.6. GPIO Mapping
Internally, PIO has a 32-bit register for the output levels of each GPIO it can drive, and another register for the output
enables (Hi/Lo-Z). On every system clock cycle, each state machine can write to some or all of the GPIOs in each of these
registers.
Figure 46. The state
machine has two
independent output
channels, one shared
by OUT/SET, and
another used by side-
set (which can happen
at any time). Three
independent mappings
(first GPIO, number of
GPIOs) control which
GPIOs OUT, SET and
side-set are directed
to. Input data is
rotated according to
which GPIO is mapped
to the LSB of the IN
data.
The write data and write masks for the output level and output enable registers come from the following sources:
•
An OUT instruction writes to up to 32 bits. Depending on the instruction’s Destination field, this is applied to either pins
or pindirs. The least-significant bit of OUT data is mapped to PINCTRL_OUT_BASE, and this mapping continues for
PINCTRL_OUT_COUNT bits, wrapping after GPIO31.
•
A SET instruction writes up to 5 bits. Depending on the instruction’s Destination field, this is applied to either pins or
pindirs. The least-significant bit of SET data is mapped to PINCTRL_SET_BASE, and this mapping continues for
PINCTRL_SET_COUNT bits, wrapping after GPIO31.
•
A side-set operation writes up to 5 bits. Depending on the register field EXECCTRL_SIDE_PINDIR, this is applied to either
pins or pindirs. The least-significant bit of side-set data is mapped to PINCTRL_SIDESET_BASE, continuing for
PINCTRL_SIDESET_COUNT pins, minus one if EXECCTRL_SIDE_EN is set.
Each OUT/SET/side-set operation writes to a contiguous range of pins, but each of these ranges is independently sized and
positioned in the 32-bit GPIO space. This is sufficiently flexible for many applications. For example, if one state machine is
implementing some interface such as an SPI on a group of pins, another state machine can run the same program,
mapped to a different group of pins, and provide a second SPI interface.
On any given clock cycle, the state machine may perform an OUT or a SET, and may simultaneously perform a side-set. The
pin mapping logic generates a 32-bit write mask and write data bus for the output level and output enable registers, based
RP2040 Datasheet
3.5. Functional Details 340