Datasheet

Note that a 'MOV' from the OSR is undefined whilst autopull is enabled; you will read either any residual data that has not
been shifted out, or a fresh word from the FIFO, depending on a race against system DMA. Likewise, a 'MOV' to the OSR
may overwrite data which has just been autopulled. However, data which you 'MOV' into the OSR will never be overwritten,
since 'MOV' updates the shift counter.
If you do need to read the OSR contents, you should perform an explicit 'PULL' of some kind. The nondeterminism
described above is the cost of the hardware managing pulls automatically. When autopull is enabled, the behaviour of
'PULL' is altered: it becomes a no-op if the OSR is full. This is to avoid a race condition against the system DMA. It behaves
as a fence: either an autopull has already taken place, in which case the 'PULL' has no effect, or the program will stall on
the 'PULL' until data becomes available in the FIFO.
'PUSH' does not need a similar behaviour, because autopush does not have the same nondeterminism.
3.5.5. Clock Dividers
PIO runs off the system clock, but this is simply too fast for many interfaces, and the number of Delay cycles which can be
inserted is limited. Some devices, such as UART, require the signalling rate to be precisely controlled and varied, and
ideally multiple state machines can be varied independently while running identical programs. Each state machine is
equipped with a clock divider, for this purpose.
Rather than slowing the system clock itself, the clock divider redefines how many system clock periods are considered to
be "one cycle", for execution purposes. It does this by generating a clock enable signal, which can pause and resume
execution on a per-system-clock-cycle basis. The clock divider generates clock enable pulses at regular intervals, so that
the state machine runs at some steady pace, potentially much slower than the system clock.
Implementing the clock dividers in this way allows interfacing between the state machines and the system to be simpler,
lower-latency, and with a smaller footprint. The state machine is completely idle on cycles where clock enable is low,
though the system can still access the state machine’s FIFOs and change its configuration.
The clock dividers are 16-bit integer, 8-bit fractional, with first-order delta-sigma for the fractional divider. The clock divisor
can vary between 1 and 65536, in increments of .
If the clock divisor is set to 1, the state machine runs on every cycle, i.e. full speed:
System Clock
CLKDIV_INT
CLKDIV_FRAC
Clock Enable
CTRL_SM_ENABLE
1
.0
Figure 43. State
machine operation
with a clock divisor of
1. Once the state
machine is enabled via
the CTRL register, its
clock enable is
asserted on every
cycle.
In general, an integer clock divisor of n will cause the state machine to run 1 cycle in every n, giving an effective clock
speed of .
System Clock
CLKDIV_INT
CLKDIV_FRAC
Clock Enable
CTRL_SM_ENABLE
2
.0
Figure 44. Integer
clock divisors yield a
periodic clock enable.
The clock divider
repeatedly counts
down from n, and
emits an enable pulse
when it reaches 1.
Fractional division will maintain a steady state division rate of , where n and f are the integer and fractional
fields of this state machine’s CLKDIV register. It does this by selectively extending some division periods from cycles to
.
RP2040 Datasheet
3.5. Functional Details 339