Datasheet

8 #define squarewave_wrap_wrap_target 0u
9 #define squarewave_wrap_wrap 1u
The squarewave_wrap example has delay cycles inserted, so that it behaves identically to the original squarewave program.
Thanks to program wrapping, these can be removed, so that the output toggles twice as fast, while maintaining an even
balance of high and low periods.
1 .program squarewave_fast
2
3 .wrap_target
4 set pins, 1 ; Drive pin high
5 set pins, 0 ; Drive pin low
6 .wrap
3.5.3. FIFO Joining
By default, each state machine possesses a 4-entry FIFO in each direction: one for data transfer from system to state
machine (TX), the other for the reverse direction (RX). However, many applications do not require bidirectional data
transfer between the system and an individual state machine, but may benefit from deeper FIFOs: in particular, high-
bandwidth interfaces such as DPI. For these cases, SHIFTCTRL_FJOIN can merge the two 4-entry FIFOs into a single 8-entry
FIFO.
Figure 40. Joinable
dual FIFO. A pair of
four-entry FIFOs,
implemented with four
data registers, a 1:4
decoder and a 4:1
multiplexer. Additional
multiplexing allows
write data and read
data to cross between
the TX and RX lanes,
so that all 8 entries
are accessible from
both ports
Another example is a UART: because the TX/CTS and RX/RTS parts a of a UART are asynchronous, they are implemented
on two separate state machines. It would be wasteful to leave half of each state machine’s FIFO resources idle. The ability
to join the two halves into just a TX FIFO for the TX/CTS state machine, or just an RX FIFO in the case of the RX/RTS state
machine, allows full utilisation. A UART equipped with an 8-deep FIFO can be left alone for twice as long between
interrupts as one with only a 4-deep FIFO.
The area and power footprint of this whole FIFO arrangement is nearly identical to a single 8-deep FIFO, but this design
covers many more use cases.
When one FIFO is increased in size (from 4 to 8), the other FIFO on that state machine is reduced to zero. For example, if
joining to TX, the RX FIFO is unavailable, and any PUSH instruction will stall. The RX FIFO will appear both RXFULL and RXEMPTY
in the FSTAT register. The converse is true if joining to RX: the TX FIFO is unavailable, and the TXFULL and TXEMPTY bits for this
state machine will both be set in FSTAT.
8 FIFO entries is sufficient for 1 word per clock through the RP2040 system DMA, provided the DMA is not slowed by
contention with other masters.
RP2040 Datasheet
3.5. Functional Details 334