Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.4.1. Features
- 2.4.2. Functional Description
- 2.4.3. Programmer’s model
- 2.4.4. System control
- 2.4.5. NVIC
- 2.4.6. MPU
- 2.4.7. Debug
- 2.4.8. List of Registers
- 2.5. Memory
- 2.6. Boot Sequence
- 2.7. Bootrom
- 2.7.1. Bootrom Source
- 2.7.2. Processor Controlled Boot Sequence
- 2.7.3. Bootrom Contents
- 2.7.4. USB Mass Storage Interface
- 2.7.5. USB PICOBOOT Interface
- 2.8. Power Supplies
- 2.9. On-Chip Voltage Regulator
- 2.10. Power Control
- 2.11. Chip-Level Reset
- 2.12. Power-On State Machine
- 2.13. Subsystem Resets
- 2.14. Clocks
- 2.14.1. Overview
- 2.14.2. Clock sources
- 2.14.2.1. Ring Oscillator
- 2.14.2.1.1. Mitigating ROSC frequency variation due to process
- 2.14.2.1.2. Mitigating ROSC frequency variation due to voltage
- 2.14.2.1.3. Mitigating ROSC frequency variation due to temperature
- 2.14.2.1.4. Automatic mitigation of ROSC frequency variation due to PVT
- 2.14.2.1.5. Automatic overclocking using the ROSC
- 2.14.2.2. Crystal Oscillator
- 2.14.2.3. External Clocks
- 2.14.2.4. Relaxation Oscillators
- 2.14.2.5. PLLs
- 2.14.2.1. Ring Oscillator
- 2.14.3. Clock Generators
- 2.14.4. Frequency Counter
- 2.14.5. Resus
- 2.14.6. Programmer’s Model
- 2.14.7. List of registers
- 2.15. Crystal Oscillator (XOSC)
- 2.16. Ring Oscillator (ROSC)
- 2.17. PLL
- 2.18. GPIO
- 2.19. Sysinfo
- 2.20. Syscfg
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. DMA
- 4.3. UART
- 4.4. I2C
- 4.4.1. Features
- 4.4.2. IP Configuration
- 4.4.3. I2C Overview
- 4.4.4. I2C Terminology
- 4.4.5. I2C Behaviour
- 4.4.6. I2C Protocols
- 4.4.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.4.8. Multiple Master Arbitration
- 4.4.9. Clock Synchronization
- 4.4.10. Operation Modes
- 4.4.11. Spike Suppression
- 4.4.12. Fast Mode Plus Operation
- 4.4.13. Bus Clear Feature
- 4.4.14. IC_CLK Frequency Configuration
- 4.4.15. DMA Controller Interface
- 4.4.16. List of Registers
- 4.5. SPI
- 4.5.1. Overview
- 4.5.2. Functional Description
- 4.5.3. Operation
- 4.5.3.1. Interface reset
- 4.5.3.2. Configuring the SSP
- 4.5.3.3. Enable PrimeCell SSP operation
- 4.5.3.4. Clock ratios
- 4.5.3.5. Programming the SSPCR0 Control Register
- 4.5.3.6. Programming the SSPCR1 Control Register
- 4.5.3.7. Frame format
- 4.5.3.8. Texas Instruments synchronous serial frame format
- 4.5.3.9. Motorola SPI frame format
- 4.5.3.10. Motorola SPI Format with SPO=0, SPH=0
- 4.5.3.11. Motorola SPI Format with SPO=0, SPH=1
- 4.5.3.12. Motorola SPI Format with SPO=1, SPH=0
- 4.5.3.13. Motorola SPI Format with SPO=1, SPH=1
- 4.5.3.14. National Semiconductor Microwire frame format
- 4.5.3.15. Examples of master and slave configurations
- 4.5.3.16. PrimeCell DMA interface
- 4.5.4. List of Registers
- 4.6. PWM
- 4.7. Timer
- 4.8. Watchdog
- 4.9. RTC
- 4.10. ADC and Temperature Sensor
- 4.11. SSI
- 4.11.1. Overview
- 4.11.2. Features
- 4.11.3. IP Modifications
- 4.11.4. Clock Ratios
- 4.11.5. Transmit and Receive FIFO Buffers
- 4.11.6. 32-Bit Frame Size Support
- 4.11.7. SSI Interrupts
- 4.11.8. Transfer Modes
- 4.11.9. Operation Modes
- 4.11.10. Partner Connection Interfaces
- 4.11.11. DMA Controller Interface
- 4.11.12. APB Interface
- 4.11.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
4.
Whether side-set writes to GPIO levels or GPIO directions. Configured by EXECCTRL_SIDE_PINDIR
In the above example, we have only one side-set data bit, and every instruction performs a side-set, so no enable bit is
required. SIDESET_COUNT would be 1, SIDE_EN would be false. SIDE_PINDIR would also be false, as we want to drive the clock
high and low, not high- and low-impedance. SIDESET_BASE would select the GPIO the clock is driven from.
3.5.2. Program Wrapping
PIO programs often have an "outer loop": they perform the same sequence of steps, repetitively, as they transfer a stream
of data between the FIFOs and the outside world. The square wave program from the introduction is a minimal example
of this:
1 .program squarewave
2 again:
3 set pins, 1 [1] ; Drive pin high and then delay for one cycle
4 set pins, 0 ; Drive pin low
5 jmp again ; Set PC to label `again`
The main body of the program drives a pin high, and then low, producing one period of a square wave. The entire program
then loops, driving a periodic output. The jump itself takes one cycle, as does each set instruction, so to keep the high and
low periods of the same duration, the set pins, 1 has a single delay cycle added, which makes the state machine idle for
one cycle before executing the set pins, 0 instruction. In total, each loop takes four cycles. There are two frustrations
here:
•
The JMP takes up space in the instruction memory that could be used for other programs
•
The extra cycle taken to execute the JMP ends up halving the maximum output rate
As the Program Counter (PC) naturally wraps to 0 when incremented past 31, we could solve the second of these by filling
the entire instruction memory with a repeating pattern of set pins, 1 and set pins, 0, but this is wasteful. State machines
have a hardware feature, configured via their EXECCTRL control register, which solves this common case.
1 .program squarewave_wrap
2
3 .wrap_target
4 set pins, 1 [1] ; Drive pin high and then delay for one cycle
5 set pins, 0 [1] ; Drive pin low and then delay for one cycle
6 .wrap
After executing an instruction from the program memory, state machines use the following logic to update PC:
1.
If the current instruction is a JMP, and the Condition is true, set PC to the Target
2.
Otherwise, if PC matches EXECCTRL_WRAP_TOP, set PC to EXECCTRL_WRAP_BOTTOM
3.
Otherwise, increment PC, or set to 0 if the current value is 31.
The .wrap_target and .wrap assembly directives are essentially labels. They export constants which can be written to the
WRAP_BOTTOM and WRAP_TOP control fields, respectively:
1 // --- squarewave_wrap ---
2
3 static const uint16_t squarewave_wrap_program[] = {
4 0xe101, // 00
5 0xe100, // 01
6 };
7
RP2040 Datasheet
3.5. Functional Details 333