Datasheet

irq set Also means set the IRQ without waiting
irq nowait Again, means set the IRQ without waiting
irq wait Means set the IRQ and wait for it to be cleared before proceeding
irq clear Means clear the IRQ
3.4.10. SET
3.4.10.1. Encoding
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SET
1 1 1 Delay/side-set Destination Data
3.4.10.2. Operation
Write immediate value Data to Destination.
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Destination:
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000: PINS
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001: X (scratch register X) 5 LSBs are set to Data, all others cleared to 0.
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010: Y (scratch register Y) 5 LSBs are set to Data, all others cleared to 0.
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011: Reserved
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100: PINDIRS
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101: Reserved
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110: Reserved
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111: Reserved
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Data: 5-bit immediate value to drive to pins or register.
This can be used to assert control signals such as a clock or chip select, or to initialise loop counters. As Data is 5 bits in
size, scratch registers can be SET to values from 0-31, which is sufficient for a 32-iteration loop.
The mapping of SET and OUT onto pins is configured independently. They may be mapped to distinct locations, for example
if one pin is to be used as a clock signal, and another for data. They may also be overlapping ranges of pins: a UART
transmitter might use SET to assert start and stop bits, and OUT instructions to shift out FIFO data to the same pins.
3.4.10.3. Assembler Syntax
set <destination>, <value>
where:
<destination> Is one of the destinations specified above.
<value> The value (see Section 3.3.3) to set (valid range 0-31)
RP2040 Datasheet
3.4. Instruction Set 331