Datasheet

Table Of Contents
<op> If present, is:
! or ~ for NOT (Note: this is always a bitwise NOT)
:: for bit reverse
<source> Is one of the sources specified above.
3.4.9. IRQ
3.4.9.1. Encoding
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRQ
1 1 0 Delay/side-set 0 Clr Wait Index
3.4.9.2. Operation
Set or clear the IRQ flag selected by Index argument.
Clear: if 1, clear the flag selected by Index, instead of raising it. If Clear is set, the Wait bit has no effect.
Wait: if 1, halt until the raised flag is lowered again, e.g. if a system interrupt handler has acknowledged the flag.
Index:
The 3 LSBs specify an IRQ index from 0-7. This IRQ flag will be set/cleared depending on the Clear bit.
If the MSB is set, the state machine ID (0…3) is added to the IRQ index, by way of modulo-4 addition on the two
LSBs. For example, state machine 2 with a flag value of 0x11 will raise flag 3, and a flag value of 0x13 will raise
flag 1.
IRQ flags 4-7 are visible only to the state machines; IRQ flags 0-3 can be routed out to system level interrupts, on either of
the PIO’s two external interrupt request lines, configured by IRQ0_INTE and IRQ1_INTE.
The modulo addition bit allows relative addressing of 'IRQ' and 'WAIT' instructions, for synchronising state machines
which are running the same program. Bit 2 (the third LSB) is unaffected by this addition.
If Wait is set, Delay cycles do not begin until after the wait period elapses.
3.4.9.3. Assembler Syntax
irq <irq_num> ( _rel )
irq set <irq_num> ( _rel )
irq nowait <irq_num> ( _rel )
irq wait <irq_num> ( _rel )
irq clear <irq_num> ( _rel )
where:
<irq_num> ( rel ) Is a value (see Section 3.3.3) specifying The irq number to wait on (0-7). If rel is present, then the
actual irq number used is calculating by replacing the low two bits of the irq number (irq_num
10
) with
the low two bits of the sum (irq_num
10
+ sm_num
10
) where sm_num
10
is the state machine number
irq Means set the IRQ without waiting
RP2040 Datasheet
3.4. Instruction Set 330