Datasheet


CAUTION
WAIT 1 IRQ x should not be used with IRQ flags presented to the interrupt controller, to avoid a race condition with a
system interrupt handler
3.4.3.3. Assembler Syntax
wait <polarity> gpio <gpio_num>
wait <polarity> pin <pin_num>
wait <polarity> irq <irq_num> ( rel )
where:
<polarity> Is a value (see Section 3.3.3) specifying the polarity (either 0 or 1)
<pin_num> Is a value (see Section 3.3.3) specifying the input pin number (as mapped by the SM input pin
mapping)
<gpio_num> Is a value (see Section 3.3.3) specifying the actual GPIO pin number
<irq_num> ( rel ) Is a value (see Section 3.3.3) specifying The irq number to wait on (0-7). If rel is present, then the
actual irq number used is calculating by replacing the low two bits of the irq number (irq_num
10
) with
the low two bits of the sum (irq_num
10
+ sm_num
10
) where sm_num
10
is the state machine number
3.4.4. IN
3.4.4.1. Encoding
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IN
0 1 0 Delay/side-set Source Bit count
3.4.4.2. Operation
Shift Bit count bits from Source into the Input Shift Register (ISR). Shift direction is configured for each state machine by
SHIFTCTRL_IN_SHIFTDIR. Additionally, increase the input shift count by Bit count, saturating at 32.
•
Source:
◦
000: PINS
◦
001: X (scratch register X)
◦
010: Y (scratch register Y)
◦
011: NULL (all zeroes)
◦
100: Reserved
◦
101: Reserved
◦
110: ISR
◦
111: OSR
•
Bit count: How many bits to shift into the ISR. 1…32 bits, 32 is encoded as 00000.
If automatic push is enabled, IN will also push the ISR contents to the RX FIFO if the push threshold is reached
RP2040 Datasheet
3.4. Instruction Set 325