Datasheet

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Often, a state machine is only transferring data in one direction. In this case the SHIFTCTRL_FJOIN option can merge the two
FIFOs into a single 8-entry FIFO going in one direction only. This is useful for high-bandwidth interfaces such as DPI.
3.2.4. Stalling
State machines may momentarily pause execution for a number of reasons:
A WAIT instruction’s condition is not yet met
A blocking PULL when the TX FIFO is empty, or a blocking PUSH when the RX FIFO is full
An IRQ WAIT instruction which has set an IRQ flag, and is waiting for it to clear
An OUT instruction when autopull is enabled, OSR has reached its shift threshold, and the TX FIFO is empty
An IN instruction when autopush is enabled, ISR reaches its shift threshold, and the RX FIFO is full
In this case, the program counter does not advance, and the state machine will continue executing this instruction on the
next cycle. If the instruction specifies some number of delay cycles before the next instruction starts, these do not begin
until after the stall clears.
NOTE
Side-set (Section 3.5.1) is not affected by stalls, and always takes place on the first cycle of the attached instruction.
3.2.5. Pin Mapping
PIO controls the output level and direction of up to 32 GPIOs, and can observe their input levels. On every system clock
cycle, each state machine may do none, one, or both of the following:
Change the level or direction of some GPIOs via an OUT or SET instruction, or read some GPIOs via an IN instruction
Change the level or direction of some GPIOs via a side-set operation
Each of these operations is on some contiguous range of GPIOs, with the base and count configured via each state
machine’s PINCTRL register. OUT, SET, IN and side-set have their own independent mappings, which are allowed to overlap.
For each individual GPIO output (level and direction separately), PIO considers all 8 writes that may have occurred on that
cycle, and applies the write from the highest-numbered state machine. If the same state machine performs a SET/OUT and
a side-set on the same GPIO simultaneously, the side-set is used. If no state machine writes to this GPIO output, its value
does not change from the previous cycle.
Generally each state machine’s outputs are mapped to a distinct group of GPIOs, implementing some peripheral interface.
3.2.6. IRQ Flags
IRQ flags are state bits which can be set or cleared by state machines or the system. There are 8 in total: all 8 are visible
to all state machines, and the lower 4 can also be masked into one of PIO’s interrupt request lines, via the IRQ0_INTE and
IRQ1_INTE control registers.
They have two main uses:
Asserting system level interrupts from a state machine program, and optionally waiting for the interrupt to be
acknowledged
Synchronising execution between two state machines
State machines interact with the flags via the IRQ and WAIT instructions.
RP2040 Datasheet
3.2. Programmer’s Model 312