Datasheet

Table Of Contents
The ISR can be automatically emptied once some number of bits have been shifted in. See Section 3.5.4
PUSH or PULL instructions can be conditioned on the input or output shift counter, respectively
On PIO reset, or the assertion of CTRL_SM_RESTART, the ISR shift counter is cleared to 0 (nothing yet shifted in), and the OSR
shift counter is initialised to 32 (nothing remaining to be shifted out). Some other instructions affect the shift counters:
PULL clears the output shift counter
PUSH clears the input shift counter
MOV OSR, x clears the output shift counter
MOV ISR, x clears the input shift counter
OUT ISR, count sets the input shift counter to count
3.2.3.4. Scratch Registers
Each state machine has two 32-bit internal scratch registers, called X and Y.
They are used as:
Source/destination for IN/OUT/SET/MOV
Source for branch conditions
For example, suppose we wanted to produce a long pulse for "1" data bits, and a short pulse for "0" data bits:
Ê1 .program ws2812_led
Ê2
Ê3 .extern entry_point
Ê4 pull
Ê5 set x, 23 ; Loop over 24 bits
Ê6 bitloop:
Ê7 set pins, 1 ; Drive pin high
Ê8 out y, 1 [5] ; Shift 1 bit out, and write it to y
Ê9 jmp !y skip ; Skip the extra delay if the bit was 0
10 nop [5]
11 skip:
12 set pins, 0 [5]
13 jmp x-- bitloop ; Jump if x nonzero, and decrement x
14 jmp entry_point
Here X is used as a loop counter, and Y is used as a temporary variable for branching on single bits from the OSR. This
program can be used to drive a WS2812 LED interface, although more compact implementations are possible (as few as
3 instructions).
MOV allows the use of the scratch registers to save/restore the shift registers if, for example, you would like to repeatedly
shift out the same sequence.
3.2.3.5. FIFOs
Each state machine has a pair of 4-word deep FIFOs, one for data transfer from system to state machine (TX), and the
other for state machine to system (RX). The TX FIFO is written to by system busmasters, such as a processor or DMA
controller, and the RX FIFO is written to by the state machine. FIFOs decouple the timing of the PIO state machines and
the system bus, allowing state machines to go for longer periods without processor intervention.
FIFOs also generate data request (DREQ) signals, which allow a system DMA controller to pace its reads/writes based on
the presence of data in an RX FIFO, or space for new data in a TX FIFO. This allows a processor to set up a long
transaction, potentially involving many kilobytes of data, which will proceed with no further processor intervention.
RP2040 Datasheet
3.2. Programmer’s Model 311