Datasheet

1 // Set the state machine running
2 hw_set_bits(&pio->ctrl, 1 << (PIO_CTRL_SM_ENABLE_LSB + 0));
The above code fragments are part of a complete application which drives a 12 MHz square wave out of GPIO 0. TO DO:
LIAM/GRAHAM: link to SDK
Most instructions are executed from the instruction memory, but there are other sources, which can be freely mixed:
•
Instructions written to a special configuration register (SMx INSTR) are immediately executed, momentarily interrupting
other execution. For example, a JMP instruction written to SMx INSTR will cause the state machine to start executing
from a different location.
•
Instructions can be executed from a register, using the MOV EXEC instruction.
•
Instructions can be executed from the output shifter, using the OUT EXEC instruction
The last of these is particularly versatile: instructions can be embedded in the stream of data passing through the FIFO.
The I2C example uses this to embed e.g. STOP and RESTART line conditions alongside normal data. In the case of MOV and OUT
EXEC, the MOV/OUT itself executes in one cycle, and the executee on the next.
3.2.3. Registers
Each state machine possesses a small number of internal registers. These hold input or output data, and temporary
values such as loop counter variables.
3.2.3.1. Output Shift Register (OSR)
Figure 38. Output Shift
Register (OSR). Data is
parcelled out 1…32
bits at a time, and
unused data is
recycled by a
bidirectional shifter.
Once empty, the OSR
is reloaded from the
TX FIFO.
The Output Shift Register (OSR) holds and shifts output data, between the TX FIFO and the pins (or other destinations,
such as the scratch registers).
•
PULL instructions pop a 32-bit word from the TX FIFO into the OSR.
•
OUT instructions shift data from the OSR to other destinations, 1…32 bits at a time.
•
The OSR fills with zeroes as data is shifted out
•
The state machine will automatically refill the OSR from the FIFO on an OUT instruction, once some total shift count
threshold is reached, if autopull is enabled
•
Shift direction can be left/right, configurable by the processor via configuration registers
For example, to stream data through the FIFO and output to the pins at a rate of one byte per two clocks:
1 .program pull_example1
2 loop:
3 out pins, 8
4 .extern entry_point
5 pull
6 out pins, 8 [1]
7 out pins, 8 [1]
8 out pins, 8
9 jmp loop
RP2040 Datasheet
3.2. Programmer’s Model 309