Datasheet

Table Of Contents
Chapter 3. PIO
3.1. Overview
Figure 36. PIO block-
level diagram. There
are two PIO blocks
with four state
machines each. The
four state machines
simultaneously
execute programs
from a shared
instruction memory.
FIFO data queues
buffer data transferred
between PIO and the
system. GPIO mapping
logic allows each
state machine to
observe and
manipulate up to 30
GPIOs.
The programmable input/output block (PIO) is a versatile hardware interface. It can support a variety of IO standards,
including:
8080 and 6800 parallel bus
I2C
3-pin I2S
SDIO
SPI, DSPI, QSPI
UART
DPI or VGA (via resistor DAC)
PIO is programmable in the same sense as a processor. There are two PIO blocks with four state machines each, that can
independently execute sequential programs to manipulate GPIOs and transfer data. Unlike a general purpose processor,
PIO state machines are highly specialised for IO, with a focus on determinism, precise timing, and close integration with
fixed-function hardware. Each state machine is equipped with:
Two 32-bit shift registers – either direction, any shift count
Two 32-bit scratch registers
4×32 bit bus FIFO in each direction (TX/RX), reconfigurable as 8×32 in a single direction
Fractional clock divider (16 integer, 8 fractional bits)
Flexible GPIO mapping
DMA interface, sustained throughput up to 1 word per clock from system DMA
RP2040 Datasheet
3.1. Overview 306