Datasheet

PERFSEL
x
Event Description
16 XIP_MAIN access,
contested
Completion of an access to the XIP_MAIN arbiter, which was previously delayed due to
an access by another master.
17 XIP_MAIN access Completion of an access to the XIP_MAIN arbiter
18 ROM access,
contested
Completion of an access to the ROM arbiter, which was previously delayed due to an
access by another master.
19 ROM access Completion of an access to the ROM arbiter
2.1.2. Atomic Register Access
Each peripheral register block is allocated 4kB of address space, with registers accessed using one of 4 methods,
selected by address decode.
•
Addr + 0x0000 : normal read write access
•
Addr + 0x1000 : atomic XOR on write
•
Addr + 0x2000 : atomic bitmask set on write
•
Addr + 0x3000 : atomic bitmask clear on write
This allows individual fields of a control register to be modified without performing a read-modify-write sequence in
software: instead the changes are posted to the peripheral, and performed in-situ. Without this capability, it is difficult to
safely access IO registers when an interrupt service routine is concurrent with code running in the foreground, or when the
two processors are running code in parallel.
The four atomic access aliases occupy a total of 16 kB. Most peripherals on RP2040 provide this functionality natively,
and atomic writes have the same timing as normal read/write access. Some peripherals (I2C, UART, SPI and SSI) instead
have this functionality added using a bus interposer, which translates upstream atomic writes into downstream read-
modify-write sequences, at the boundary of the peripheral. This extends the access time by two system clock cycles.
The SIO (Section 2.3.1), a single-cycle IO block attached directly to the cores' IO ports, does not support atomic accesses
at the bus level, although some individual registers (e.g. GPIO) have set/clear/xor aliases.
2.1.3. APB Bridge
The APB bridge interfaces the high-speed main AHB-Lite interconnect to the lower-bandwidth peripherals. Whilst the AHB-
Lite fabric offers zero-wait-state access everywhere, APB accesses have a cycle penalty:
•
APB bus accesses take two cycles minimum (setup phase and access phase)
•
The bridge adds an additional cycle to read accesses, as the bus request and response are registered
•
The bridge adds two additional cycles to write accesses, as the APB setup phase can not begin until the AHB-Lite
write data is valid
As a result, the throughput of the APB portion of the bus fabric is somewhat lower than the AHB-Lite portion. However,
there is more than sufficient bandwidth to saturate the APB serial peripherals.
2.1.4. Narrow IO Register Writes
Memory-mapped IO registers on RP2040 ignore the width of bus read/write accesses. They treat all writes as though they
were 32 bits in size. This means software can not use byte or halfword writes to modify part of an IO register: any write to
an address where the 30 address MSBs match the register address will affect the contents of the entire register.
To update part of an IO register, without a read-modify-write sequence, the best solution on RP2040 is atomic
RP2040 Datasheet
2.1. Bus Fabric 24