Datasheet

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NOTE
Priority arbitration only applies to multiple masters attempting to access the same slave on the same cycle. Accesses
to different slaves, e.g. different SRAM banks, can proceed simultaneously.
When accessing a slave with zero wait states, such as SRAM (i.e. can be accessed once per system clock cycle), high-
priority masters will never observe any slowdown or other timing effects caused by accesses from low-priority masters.
This allows guaranteed latency and throughput for hard real time use cases; it does however mean a low-priority master
may get stalled until there is a free cycle.
2.1.1.2. Bus Performance Counters
The performance counters automatically count accesses to the main AHB-Lite crossbar arbiters. This can assist in
diagnosing performance issues, in high-traffic use cases.
There are four performance counters. Each is a 24-bit saturating counter. Counter values can be read from
BUSCTRL_PERFCTRx, and cleared by writing any value to BUSCTRL_PERFCTRx. Each counter can count one of the 20 available
events at a time, as selected by BUSCTRL_PERFSELx. The available bus events are:
PERFSEL
x
Event Description
0 APB access,
contested
Completion of an access to the APB arbiter (which is upstream of all APB peripherals),
which was previously delayed due to an access by another master.
1 APB access Completion of an access to the APB arbiter
2 FASTPERI access,
contested
Completion of an access to the FASTPERI arbiter (which is upstream of PIOs, DMA
config port, USB, XIP aux FIFO port), which was previously delayed due to an access by
another master.
3 FASTPERI access Completion of an access to the FASTPERI arbiter
4 SRAM5 access,
contested
Completion of an access to the SRAM5 arbiter, which was previously delayed due to an
access by another master.
5 SRAM5 access Completion of an access to the SRAM5 arbiter
6 SRAM4 access,
contested
Completion of an access to the SRAM4 arbiter, which was previously delayed due to an
access by another master.
7 SRAM4 access Completion of an access to the SRAM4 arbiter
8 SRAM3 access,
contested
Completion of an access to the SRAM3 arbiter, which was previously delayed due to an
access by another master.
9 SRAM3 access Completion of an access to the SRAM3 arbiter
10 SRAM2 access,
contested
Completion of an access to the SRAM2 arbiter, which was previously delayed due to an
access by another master.
11 SRAM2 access Completion of an access to the SRAM2 arbiter
12 SRAM1 access,
contested
Completion of an access to the SRAM1 arbiter, which was previously delayed due to an
access by another master.
13 SRAM1 access Completion of an access to the SRAM1 arbiter
14 SRAM0 access,
contested
Completion of an access to the SRAM0 arbiter, which was previously delayed due to an
access by another master.
15 SRAM0 access Completion of an access to the SRAM0 arbiter
RP2040 Datasheet
2.1. Bus Fabric 23