Datasheet

Table Of Contents
Function
QSPI SD2 XIP SD2 SIO
QSPI SD3 XIP SD3 SIO
Table 277. GPIO QSPI
Bank function
descriptions
Function Name Description
XIP Connection to the synchronous serial interface (SSI) inside the flash execute in place (XIP) subsystem.
This allows processors to execute code directly from an external SPI, Dual-SPI or Quad-SPI flash
SIO
Software control of GPIO, from the single-cycle IO (SIO) block. The SIO function (F5) must be selected for
the processors to drive a GPIO, but the input is always connected, so software can check the state of
GPIOs at any time. The QSPI IOs are controlled via the SIO_GPIO_HI_x registers, and are mapped to register
bits in the order SCK, CSn, SD0, SD1, SD2, SD3, starting at the LSB.
The six QSPI Bank GPIO pins are typically used by the XIP peripheral to communicate with an external flash device.
However, there are two scenarios where the pins can be used as software-controlled GPIOs:
If a SPI or Dual-SPI flash device is used for execute-in-place, then the SD2 and SD3 pins are not used for flash
access, and can be used for other GPIO functions on the circuit board.
If RP2040 is used in a flashless configuration (USB boot only), then all six pins can be used for software-controlled
GPIO functions
2.18.3. Interrupts
An interrupt can be generated for every GPIO pin in four scenarios:
Level High: the GPIO pin is a logical 1
Level Low: the GPIO pin is a logical 0
Edge High: the GPIO has transitioned from a logical 0 to a logical 1
Edge Low: the GPIO has transitioned from a logical 1 to a logical 0
The level interrupts are not latched. This means that if the pin is a logical 1 and the level high interrupt is active, it will
become inactive as soon as the pin changes to a logical 0. The edge interrupts are stored in the INTR register and can be
cleared by writing to the INTR register.
There are enable (PROC0_INTE0), status (PROC0_INTS0), and force (PROC0_INTF0) registers for three interrupt
destinations: core 0, core 1, and dormant_wake. Dormant wake is used to wake the ROSC or XOSC up from dormant
mode. See Section 2.10.5.2 for more information on dormant mode.
All interrupts are ORed together per-bank per-destination resulting in a total of six GPIO interrupts:
io_bank0_to_dormant_wake
io_bank0_to_proc0
io_bank0_to_proc1
io_bank1_to_dormant_wake
io_bank1_to_proc0
io_bank1_to_proc1
This means the user can watch for several GPIO events at once.
RP2040 Datasheet
2.18. GPIO 211