Datasheet

Description
Controls the PLL power modes.
Table 271. PWR
Register
Bits Name Description Type Reset
31:6 Reserved. - - -
5 VCOPD PLL VCO powerdown
To save power set high when PLL output not required or
bypass=1.
RW 0x1
4 Reserved. - - -
3 POSTDIVPD PLL post divider powerdown
To save power set high when PLL output not required or
bypass=1.
RW 0x1
2 DSMPD PLL DSM powerdown
Nothing is achieved by setting this low.
RW 0x1
1 Reserved. - - -
0 PD PLL powerdown
To save power set high when PLL output not required.
RW 0x1
FBDIV_INT Register
Description
Feedback divisor
(note: this PLL does not support fractional division)
Table 272. FBDIV_INT
Register
Bits Name Description Type Reset
31:12 Reserved. - - -
11:0 NONAME see ctrl reg description for constraints RW 0x000
PRIM Register
Description
Controls the PLL post dividers for the primary output
(note: this PLL does not have a secondary output)
the primary output is driven from VCO divided by postdiv1*postdiv2
Table 273. PRIM
Register
Bits Name Description Type Reset
31:19 Reserved. - - -
18:16 POSTDIV1 divide by 1-7 RW 0x7
15 Reserved. - - -
14:12 POSTDIV2 divide by 1-7 RW 0x7
11:0 Reserved. - - -
2.18. GPIO
RP2040 Datasheet
2.18. GPIO 207