Datasheet

50 hw_clear_bits(&pll->pwr, power);
51
52 // Wait for PLL to lock
53 while (!(pll->cs & PLL_CS_LOCK_BITS)) tight_loop_contents();
54
55 // Set up post dividers - div1 feeds into div2 so if div1 is 5 and div2 is 2 then you get
Ê a divide by 10
56 uint32_t pdiv = (post_div1 << PLL_PRIM_POSTDIV1_LSB) |
57 (post_div2 << PLL_PRIM_POSTDIV2_LSB);
58 pll->prim = pdiv;
59
60 // Turn on post divider
61 hw_clear_bits(&pll->pwr, PLL_PWR_POSTDIVPD_BITS);
Note the VCO is turned on first, followed by the post dividers so the PLL does not output a dirty clock while the VCO is
locking.
2.17.4. List of registers
Table 269. List of PLL
registers
Offset Name Info
0x0 CS Control and Status
0x4 PWR Controls the PLL power modes.
0x8 FBDIV_INT Feedback divisor
0xc PRIM Controls the PLL post dividers for the primary output
CS Register
Description
Control and Status
GENERAL CONSTRAINTS:
Reference clock frequency min=5MHz, max=800MHz
Feedback divider min=16, max=320
VCO frequency min=400MHz, max=1600MHz
Table 270. CS Register
Bits Name Description Type Reset
31 LOCK PLL is locked RO 0x0
30:9 Reserved. - - -
8 BYPASS Passes the reference clock to the output instead of the
divided VCO.
The VCO continues to run so the user can switch between
the reference
clock and the divided VCO but the output will glitch when
doing so.
RW 0x0
7:6 Reserved. - - -
5:0 REFDIV Divides the PLL input reference clock.
Behaviour is undefined for div=0.
PLL output will be unpredictable during refdiv changes, wait
for lock=1 before using it.
RW 0x01
PWR Register
RP2040 Datasheet
2.17. PLL 206