Datasheet

The pll_init function in the Pico SDK, which we will examine below, asserts that all of these conditions are true before
attempting to configure the PLL.
The Pico SDK defines the PLL control registers as a struct. It then maps them into memory for each instance of the PLL.
Pico SDK: https://github.com/raspberrypi/pico-sdk/tree/pre_release/src/rp2040/hardware_structs/include/hardware/structs/pll.h Lines 14 - 22
14 typedef struct {
15 io_rw_32 cs;
16 io_rw_32 pwr;
17 io_rw_32 fbdiv_int;
18 io_rw_32 prim;
19 } pll_hw_t;
20
21 #define pll_sys_hw ((pll_hw_t *const)PLL_SYS_BASE)
22 #define pll_usb_hw ((pll_hw_t *const)PLL_USB_BASE)
The Pico SDK defines pll_init which is used to configure, or reconfigure a PLL. It starts by clearing any previous power
state in the PLL, then calculates the appropriate feedback divider value. There are assertions to check these values satisfy
the constraints above.
Pico SDK: https://github.com/raspberrypi/pico-sdk/tree/pre_release/src/rp2_common/hardware_pll/pll.c Lines 14 - 24
14 void pll_init(PLL pll, uint32_t refdiv, uint32_t vco_freq, uint32_t post_div1, uint8_t
Ê post_div2) {
15 // Turn off PLL in case it is already running
16 pll->pwr = 0xffffffff;
17 pll->fbdiv_int = 0;
18
19 uint32_t ref_mhz = XOSC_MHZ / refdiv;
20 pll->cs = refdiv;
21
22 // What are we multiplying the reference clock by to get the vco freq
23 // (The regs are called div, because you divide the vco output and compare it to the
Ê refclk)
24 uint32_t fbdiv = vco_freq / (ref_mhz * MHZ);
The programming sequence for the PLL is as follows:
•
Program the reference clock divider (is a divide by 1 in the RP2040 case)
•
Program the feedback divider
•
Turn on the main power and VCO
•
Wait for the VCO to lock (i.e. keep its output frequency stable)
•
Set up post dividers and turn them on
Pico SDK: https://github.com/raspberrypi/pico-sdk/tree/pre_release/src/rp2_common/hardware_pll/pll.c Lines 40 - 61
40 // Check that reference frequency is no greater than vco / 16
41 assert(ref_mhz <= (vco_freq / 16));
42
43 // Put calculated value into feedback divider
44 pll->fbdiv_int = fbdiv;
45
46 // Turn on PLL
47 uint32_t power = PLL_PWR_PD_BITS | // Main power
48 PLL_PWR_VCOPD_BITS; // VCO Power
49
RP2040 Datasheet
2.17. PLL 205