Datasheet

Table 266. STATUS
Register
Bits Name Description Type Reset
31 STABLE Oscillator is running and stable RO 0x0
30:25 Reserved. - - -
24 BADWRITE An invalid value has been written to CTRL_ENABLE or
CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT
WC 0x0
23:17 Reserved. - - -
16 DIV_RUNNING post-divider is running RO -
15:13 Reserved. - - -
12 ENABLED Oscillator is enabled but not necessarily running and stable RO -
11:0 Reserved. - - -
RANDOMBIT Register
Description
This just reads the state of the oscillator output so randomness is compromised if the ring
oscillator is stopped or run at a harmonic of the bus frequency
Table 267.
RANDOMBIT Register
Bits Name Description Type Reset
31:1 Reserved. - - -
0 NONAME RO 0x1
COUNT Register
Description
Can be used for short software pauses when setting up time sensitive hardware.
Table 268. COUNT
Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7:0 NONAME RW 0x00
2.17. PLL
2.17.1. Overview
The PLL is designed to take a reference clock, and multiply it using a VCO (Voltage Controlled Oscillator) with a feedback
loop. The VCO must run at high frequencies (between 400 and 1600 MHz), so there are two dividers, known as post
dividers that can divide the VCO frequency before it is distributed to the clock generators on the chip.
There are two PLLs in RP2040. They are:
•
pll_sys - Used to generate up to a 133 MHz system clock
•
pll_usb - Used to generate a 48 MHz USB reference clock
RP2040 Datasheet
2.17. PLL 201