Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.4.1. Features
- 2.4.2. Functional Description
- 2.4.3. Programmer’s model
- 2.4.4. System control
- 2.4.5. NVIC
- 2.4.6. MPU
- 2.4.7. Debug
- 2.4.8. List of Registers
- 2.5. Memory
- 2.6. Boot Sequence
- 2.7. Bootrom
- 2.7.1. Bootrom Source
- 2.7.2. Processor Controlled Boot Sequence
- 2.7.3. Bootrom Contents
- 2.7.4. USB Mass Storage Interface
- 2.7.5. USB PICOBOOT Interface
- 2.8. Power Supplies
- 2.9. On-Chip Voltage Regulator
- 2.10. Power Control
- 2.11. Chip-Level Reset
- 2.12. Power-On State Machine
- 2.13. Subsystem Resets
- 2.14. Clocks
- 2.14.1. Overview
- 2.14.2. Clock sources
- 2.14.2.1. Ring Oscillator
- 2.14.2.1.1. Mitigating ROSC frequency variation due to process
- 2.14.2.1.2. Mitigating ROSC frequency variation due to voltage
- 2.14.2.1.3. Mitigating ROSC frequency variation due to temperature
- 2.14.2.1.4. Automatic mitigation of ROSC frequency variation due to PVT
- 2.14.2.1.5. Automatic overclocking using the ROSC
- 2.14.2.2. Crystal Oscillator
- 2.14.2.3. External Clocks
- 2.14.2.4. Relaxation Oscillators
- 2.14.2.5. PLLs
- 2.14.2.1. Ring Oscillator
- 2.14.3. Clock Generators
- 2.14.4. Frequency Counter
- 2.14.5. Resus
- 2.14.6. Programmer’s Model
- 2.14.7. List of registers
- 2.15. Crystal Oscillator (XOSC)
- 2.16. Ring Oscillator (ROSC)
- 2.17. PLL
- 2.18. GPIO
- 2.19. Sysinfo
- 2.20. Syscfg
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. DMA
- 4.3. UART
- 4.4. I2C
- 4.4.1. Features
- 4.4.2. IP Configuration
- 4.4.3. I2C Overview
- 4.4.4. I2C Terminology
- 4.4.5. I2C Behaviour
- 4.4.6. I2C Protocols
- 4.4.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.4.8. Multiple Master Arbitration
- 4.4.9. Clock Synchronization
- 4.4.10. Operation Modes
- 4.4.11. Spike Suppression
- 4.4.12. Fast Mode Plus Operation
- 4.4.13. Bus Clear Feature
- 4.4.14. IC_CLK Frequency Configuration
- 4.4.15. DMA Controller Interface
- 4.4.16. List of Registers
- 4.5. SPI
- 4.5.1. Overview
- 4.5.2. Functional Description
- 4.5.3. Operation
- 4.5.3.1. Interface reset
- 4.5.3.2. Configuring the SSP
- 4.5.3.3. Enable PrimeCell SSP operation
- 4.5.3.4. Clock ratios
- 4.5.3.5. Programming the SSPCR0 Control Register
- 4.5.3.6. Programming the SSPCR1 Control Register
- 4.5.3.7. Frame format
- 4.5.3.8. Texas Instruments synchronous serial frame format
- 4.5.3.9. Motorola SPI frame format
- 4.5.3.10. Motorola SPI Format with SPO=0, SPH=0
- 4.5.3.11. Motorola SPI Format with SPO=0, SPH=1
- 4.5.3.12. Motorola SPI Format with SPO=1, SPH=0
- 4.5.3.13. Motorola SPI Format with SPO=1, SPH=1
- 4.5.3.14. National Semiconductor Microwire frame format
- 4.5.3.15. Examples of master and slave configurations
- 4.5.3.16. PrimeCell DMA interface
- 4.5.4. List of Registers
- 4.6. PWM
- 4.7. Timer
- 4.8. Watchdog
- 4.9. RTC
- 4.10. ADC and Temperature Sensor
- 4.11. SSI
- 4.11.1. Overview
- 4.11.2. Features
- 4.11.3. IP Modifications
- 4.11.4. Clock Ratios
- 4.11.5. Transmit and Receive FIFO Buffers
- 4.11.6. 32-Bit Frame Size Support
- 4.11.7. SSI Interrupts
- 4.11.8. Transfer Modes
- 4.11.9. Operation Modes
- 4.11.10. Partner Connection Interfaces
- 4.11.11. DMA Controller Interface
- 4.11.12. APB Interface
- 4.11.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
Description
freqa & freqb control the frequency by controlling the drive strength of each stage
The drive strength of each stage is given by:
ds_stage[n] = 1+dsn[0]+dsn[1]+dsn[2]
To calculate the frequency to a first approximation:
for range=0: freq = fbase0 * 4/4 *
(8+ds_stage[0]+ds_stage[1]+ds_stage[2]+ds_stage[3]+ds_stage[4]+ds_stage[5]+ds_stage[6]+ds_stage[7])/8
for range=1: freq = fbase0 * 4/3 * (6+ds_stage[0]+ds_stage[1]+ds_stage[2]+ds_stage[3]+ds_stage[4]+ds_stage[5])/6
for range=2: freq = fbase0 * 4/2 * (4+ds_stage[0]+ds_stage[1]+ds_stage[2]+ds_stage[3])/4
for range=3: freq = fbase0 * 4/1 * (2+ds_stage[0]+ds_stage[1])/2
where fbase0 is the frequency for range0 with no ds bits set
fbase0 will depend on temperature, voltage and process parameters.
fbase0 pre-layout estimate is 25-100MHz. This will be refined when final layout is available
If fbase0=50MHz then, to a first approximation:
for range=0: freq = 50 - 200 MHz in 32 unequal steps
for range=1: freq = 70 - 280 MHz in 24 unequal steps
for range=2: freq = 100 - 400 MHz in 16 unequal steps
for range=3: freq = 200 - 800 MHz in 8 unequal steps
In the higher ranges fewer stages contribute to the frequency but the
generated clock propagates through the unused stages so their drive
strengths should be set to the maximum.
Table 261. FREQA
Register
Bits Name Description Type Reset
31:16 PASSWD Set to 0x9696 to apply the settings
Any other value in this field will set all drive strengths to 0
RW 0x0000
15 Reserved. - - -
14:12 DS3 Stage 3 drive strength RW 0x0
11 Reserved. - - -
10:8 DS2 Stage 2 drive strength RW 0x0
7 Reserved. - - -
6:4 DS1 Stage 1 drive strength RW 0x0
3 Reserved. - - -
2:0 DS0 Stage 0 drive strength RW 0x0
FREQB Register
Description
For detailed description see freqa register
Table 262. FREQB
Register
Bits Name Description Type Reset
31:16 PASSWD Set to 0x9696 to apply the settings
Any other value in this field will set all drive strengths to 0
RW 0x0000
15 Reserved. - - -
14:12 DS7 Stage 7 drive strength RW 0x0
11 Reserved. - - -
10:8 DS6 Stage 6 drive strength RW 0x0
7 Reserved. - - -
6:4 DS5 Stage 5 drive strength RW 0x0
RP2040 Datasheet
2.16. Ring Oscillator (ROSC) 199