Datasheet

Bits Name Description Type Reset
10 KILL Asynchronously kills the clock generator RW 0x0
9:8 Reserved. - - -
7:5 AUXSRC Selects the auxiliary clock source, will glitch when
switching
0x0 -> clksrc_pll_usb
0x1 -> clksrc_pll_sys
0x2 -> rosc_clksrc_ph
0x3 -> xosc_clksrc
0x4 -> clksrc_gpin0
0x5 -> clksrc_gpin1
RW 0x0
4:0 Reserved. - - -
CLK_RTC_DIV Register
Description
Clock divisor, can be changed on-the-fly
Table 228.
CLK_RTC_DIV Register
Bits Name Description Type Reset
31:8 INT Integer component of the divisor, 0 -> divide by 2^16 RW 0x000001
7:0 FRAC Fractional component of the divisor RW 0x00
CLK_RTC_SELECTED Register
Description
Indicates which src is currently selected (one-hot)
Table 229.
CLK_RTC_SELECTED
Register
Bits Name Description Type Reset
31:0 NONAME RO 0x00000001
CLK_SYS_RESUS_CTRL Register
Table 230.
CLK_SYS_RESUS_CTR
L Register
Bits Name Description Type Reset
31:17 Reserved. - - -
16 CLEAR For clearing the resus after the fault that triggered it has
been corrected
RW 0x0
15:13 Reserved. - - -
12 FRCE Force a resus, for test purposes only RW 0x0
11:9 Reserved. - - -
8 ENABLE Enable resus RW 0x0
7:0 TIMEOUT This is expressed as a number of clk_ref cycles
and must be >= 2x clk_ref_freq/min_clk_tst_freq
RW 0xff
CLK_SYS_RESUS_STATUS Register
RP2040 Datasheet
2.14. Clocks 183