Datasheet

Bits Name Description Type Reset
7:5 AUXSRC Selects the auxiliary clock source, will glitch when
switching
0x0 -> clksrc_pll_usb
0x1 -> clksrc_pll_sys
0x2 -> rosc_clksrc_ph
0x3 -> xosc_clksrc
0x4 -> clksrc_gpin0
0x5 -> clksrc_gpin1
RW 0x0
4:0 Reserved. - - -
CLK_USB_DIV Register
Description
Clock divisor, can be changed on-the-fly
Table 222.
CLK_USB_DIV Register
Bits Name Description Type Reset
31:10 Reserved. - - -
9:8 INT Integer component of the divisor, 0 -> divide by 2^16 RW 0x1
7:0 Reserved. - - -
CLK_USB_SELECTED Register
Description
Indicates which src is currently selected (one-hot)
Table 223.
CLK_USB_SELECTED
Register
Bits Name Description Type Reset
31:0 NONAME RO 0x00000001
CLK_ADC_CTRL Register
Description
Clock control, can be changed on-the-fly (except for auxsrc)
Table 224.
CLK_ADC_CTRL
Register
Bits Name Description Type Reset
31:21 Reserved. - - -
20 NUDGE An edge on this signal shifts the phase of the output by 1
cycle of the input clock
This can be done at any time
RW 0x0
19:18 Reserved. - - -
17:16 PHASE This delays the enable signal by up to 3 cycles of the input
clock
This must be set before the clock is enabled to have any
effect
RW 0x0
15:12 Reserved. - - -
11 ENABLE Starts and stops the clock generator cleanly RW 0x0
10 KILL Asynchronously kills the clock generator RW 0x0
RP2040 Datasheet
2.14. Clocks 181