Datasheet

Bits Name Description Type Reset
4:0 Reserved. - - -
CLK_GPOUT3_DIV Register
Description
Clock divisor, can be changed on-the-fly
Table 211.
CLK_GPOUT3_DIV
Register
Bits Name Description Type Reset
31:8 INT Integer component of the divisor, 0 -> divide by 2^16 RW 0x000001
7:0 FRAC Fractional component of the divisor RW 0x00
CLK_GPOUT3_SELECTED Register
Description
Indicates which src is currently selected (one-hot)
Table 212.
CLK_GPOUT3_SELECT
ED Register
Bits Name Description Type Reset
31:0 NONAME RO 0x00000001
CLK_REF_CTRL Register
Description
Clock control, can be changed on-the-fly (except for auxsrc)
Table 213.
CLK_REF_CTRL
Register
Bits Name Description Type Reset
31:7 Reserved. - - -
6:5 AUXSRC Selects the auxiliary clock source, will glitch when
switching
0x0 -> clksrc_pll_usb
0x1 -> clksrc_gpin0
0x2 -> clksrc_gpin1
RW 0x0
4:2 Reserved. - - -
1:0 SRC Selects the clock source glitchlessly, can be changed on-
the-fly
0x0 -> rosc_clksrc_ph
0x1 -> clksrc_clk_ref_aux
0x2 -> xosc_clksrc
RW -
CLK_REF_DIV Register
Description
Clock divisor, can be changed on-the-fly
Table 214.
CLK_REF_DIV Register
Bits Name Description Type Reset
31:10 Reserved. - - -
9:8 INT Integer component of the divisor, 0 -> divide by 2^16 RW 0x1
7:0 Reserved. - - -
RP2040 Datasheet
2.14. Clocks 178