Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.4.1. Features
- 2.4.2. Functional Description
- 2.4.3. Programmer’s model
- 2.4.4. System control
- 2.4.5. NVIC
- 2.4.6. MPU
- 2.4.7. Debug
- 2.4.8. List of Registers
- 2.5. Memory
- 2.6. Boot Sequence
- 2.7. Bootrom
- 2.7.1. Bootrom Source
- 2.7.2. Processor Controlled Boot Sequence
- 2.7.3. Bootrom Contents
- 2.7.4. USB Mass Storage Interface
- 2.7.5. USB PICOBOOT Interface
- 2.8. Power Supplies
- 2.9. On-Chip Voltage Regulator
- 2.10. Power Control
- 2.11. Chip-Level Reset
- 2.12. Power-On State Machine
- 2.13. Subsystem Resets
- 2.14. Clocks
- 2.14.1. Overview
- 2.14.2. Clock sources
- 2.14.2.1. Ring Oscillator
- 2.14.2.1.1. Mitigating ROSC frequency variation due to process
- 2.14.2.1.2. Mitigating ROSC frequency variation due to voltage
- 2.14.2.1.3. Mitigating ROSC frequency variation due to temperature
- 2.14.2.1.4. Automatic mitigation of ROSC frequency variation due to PVT
- 2.14.2.1.5. Automatic overclocking using the ROSC
- 2.14.2.2. Crystal Oscillator
- 2.14.2.3. External Clocks
- 2.14.2.4. Relaxation Oscillators
- 2.14.2.5. PLLs
- 2.14.2.1. Ring Oscillator
- 2.14.3. Clock Generators
- 2.14.4. Frequency Counter
- 2.14.5. Resus
- 2.14.6. Programmer’s Model
- 2.14.7. List of registers
- 2.15. Crystal Oscillator (XOSC)
- 2.16. Ring Oscillator (ROSC)
- 2.17. PLL
- 2.18. GPIO
- 2.19. Sysinfo
- 2.20. Syscfg
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. DMA
- 4.3. UART
- 4.4. I2C
- 4.4.1. Features
- 4.4.2. IP Configuration
- 4.4.3. I2C Overview
- 4.4.4. I2C Terminology
- 4.4.5. I2C Behaviour
- 4.4.6. I2C Protocols
- 4.4.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.4.8. Multiple Master Arbitration
- 4.4.9. Clock Synchronization
- 4.4.10. Operation Modes
- 4.4.11. Spike Suppression
- 4.4.12. Fast Mode Plus Operation
- 4.4.13. Bus Clear Feature
- 4.4.14. IC_CLK Frequency Configuration
- 4.4.15. DMA Controller Interface
- 4.4.16. List of Registers
- 4.5. SPI
- 4.5.1. Overview
- 4.5.2. Functional Description
- 4.5.3. Operation
- 4.5.3.1. Interface reset
- 4.5.3.2. Configuring the SSP
- 4.5.3.3. Enable PrimeCell SSP operation
- 4.5.3.4. Clock ratios
- 4.5.3.5. Programming the SSPCR0 Control Register
- 4.5.3.6. Programming the SSPCR1 Control Register
- 4.5.3.7. Frame format
- 4.5.3.8. Texas Instruments synchronous serial frame format
- 4.5.3.9. Motorola SPI frame format
- 4.5.3.10. Motorola SPI Format with SPO=0, SPH=0
- 4.5.3.11. Motorola SPI Format with SPO=0, SPH=1
- 4.5.3.12. Motorola SPI Format with SPO=1, SPH=0
- 4.5.3.13. Motorola SPI Format with SPO=1, SPH=1
- 4.5.3.14. National Semiconductor Microwire frame format
- 4.5.3.15. Examples of master and slave configurations
- 4.5.3.16. PrimeCell DMA interface
- 4.5.4. List of Registers
- 4.6. PWM
- 4.7. Timer
- 4.8. Watchdog
- 4.9. RTC
- 4.10. ADC and Temperature Sensor
- 4.11. SSI
- 4.11.1. Overview
- 4.11.2. Features
- 4.11.3. IP Modifications
- 4.11.4. Clock Ratios
- 4.11.5. Transmit and Receive FIFO Buffers
- 4.11.6. 32-Bit Frame Size Support
- 4.11.7. SSI Interrupts
- 4.11.8. Transfer Modes
- 4.11.9. Operation Modes
- 4.11.10. Partner Connection Interfaces
- 4.11.11. DMA Controller Interface
- 4.11.12. APB Interface
- 4.11.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
Offset Name Info
0x48 CLK_PERI_CTRL Clock control, can be changed on-the-fly (except for auxsrc)
0x50 CLK_PERI_SELECTED Indicates which src is currently selected (one-hot)
0x54 CLK_USB_CTRL Clock control, can be changed on-the-fly (except for auxsrc)
0x58 CLK_USB_DIV Clock divisor, can be changed on-the-fly
0x5c CLK_USB_SELECTED Indicates which src is currently selected (one-hot)
0x60 CLK_ADC_CTRL Clock control, can be changed on-the-fly (except for auxsrc)
0x64 CLK_ADC_DIV Clock divisor, can be changed on-the-fly
0x68 CLK_ADC_SELECTED Indicates which src is currently selected (one-hot)
0x6c CLK_RTC_CTRL Clock control, can be changed on-the-fly (except for auxsrc)
0x70 CLK_RTC_DIV Clock divisor, can be changed on-the-fly
0x74 CLK_RTC_SELECTED Indicates which src is currently selected (one-hot)
0x78 CLK_SYS_RESUS_CTRL
0x7c CLK_SYS_RESUS_STATUS
0x80 FC0_REF_KHZ Reference clock frequency in kHz
0x84 FC0_MIN_KHZ Minimum pass frequency in kHz. This is optional. Set to 0 if you
are not using the pass/fail flags
0x88 FC0_MAX_KHZ Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff
if you are not using the pass/fail flags
0x8c FC0_DELAY Delays the start of frequency counting to allow the mux to settle
Delay is measured in multiples of the reference clock period
0x90 FC0_INTERVAL The test interval is 0.98us * 2interval, but let’s call it 1us *
2interval
The default gives a test interval of 250us
0x94 FC0_SRC Clock sent to frequency counter, set to 0 when not required
Writing to this register initiates the frequency count
0x98 FC0_STATUS Frequency counter status
0x9c FC0_RESULT Result of frequency measurement, only valid when status_done=1
0xa0 WAKE_EN0 enable clock in wake mode
0xa4 WAKE_EN1 enable clock in wake mode
0xa8 SLEEP_EN0 enable clock in sleep mode
0xac SLEEP_EN1 enable clock in sleep mode
0xb0 ENABLED0 indicates the state of the clock enable
0xb4 ENABLED1 indicates the state of the clock enable
0xb8 INTR Raw Interrupts
0xbc INTE Interrupt Enable
0xc0 INTF Interrupt Force
0xc4 INTS Interrupt status after masking & forcing
RP2040 Datasheet
2.14. Clocks 173